Jack,
When I was designing high voltage boards I simply relied on the electric strength spec of the dielectric that I was using and rounded up for impedance/dfm/design purposes. This was for approx. 1kV boards, but as I look at a typical FR4 spec, it doesn't look like this should be a problem with ratings being over 1kV per mil of FR4 thickness. As I recall the clearance/creepage spec was always harder to meet. I would recommend seeking the answer for your material requirements from someone in your supply chain who has access to these specifications.
And I would definitely agree on making sure if your voltage requirement is peak-peak or DC.
Good luck.
Dick Hatano
PCB Designer
3855 Ruffin Road, San Diego, CA 92123-1813 USA
Direct 858.244.3392 | Fax 858.836.3400
[log in to unmask]
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Jack Olson
Sent: Friday, June 20, 2014 11:43 AM
To: [log in to unmask]
Subject: Re: [DC] z-axis separation for high voltage
Thanks for the background on Table 6-1, Dieter!
I still maintain that those numbers were intended as minimums ACROSS a laminate (creepage) and that the minimum THROUGH a laminate should be smaller.
I just don't know where to go to get that number
The material slash sheets list HUGE numbers, but I don't think they were intended to be used as design parameters
but thanks,
Jack
On Fri, Jun 20, 2014 at 12:36 PM, Dieter Bergman <[log in to unmask]>
wrote:
> Hi Jack,
>
> When Table 6-1 was being developed we initially thought that an
> increase in voltage would require an increase in spacing. There was an
> IEC committee that dealt with creepage distances and I was lectured by
> their chairman on Passions Law of Physics which says that " a clean
> air gap dielectric spacing will sustain 300 volts peak to peak without spark over or corona".
> This was proved by the German Post Office who had a separation of
> .001" and passed all the tests. We tried to show that in the table
> initially, however since you can't guarantee a clean air gap the
> committee felt more comfortable in having different clearance graduations.
>
> When it got to voltages over 300 or 500 volts it became a best
> estimate. I tried to get people who designed in that domain to provide
> input, but in the end I was told that based on the environment that
> the product had to work in they started with a conservative spacing
> and then reduced the spacing where ever possible. So the table became
> what it is today. The initial theory was for two conductors opposite
> each other on the surface with a clean air gap. If the electrodes are
> internally or on opposite layers the air dielectric is replaced by the
> resin or reinforcement. We have seen multilayer flex with .001"
> Polyimide laminate sustain quite a high voltage between two conductive layers.
>
> The fabrication process also plays a role as does moisture, however
> the test coupons are well known and can verify that the board product,
> as produced, will survive
>
> Good luck.
> Best regards,
> Dieter
>
>
> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
> Jack Olson
> Sent: Friday, June 20, 2014 10:55 AM
> To: DesignerCouncil
> Subject: Re: [DC] z-axis separation for high voltage
>
> Thanks for taking the time to respond (and to everyone else who
> responded too), and I understand your point about derating, but I am
> more focused on the STARTING clearance for 1700V,
>
> IPC Table 6-1 gives me something slightly over 125 mils, and my board
> is only 62 mil thickness, about half!
> I wasn't initially worried
> because if you look at the slash sheets for dielectric material, its
> more in the KV range PER MIL but now I'm starting to wonder...
>
> Where can I learn more about this?
>
>
> On Fri, Jun 20, 2014 at 10:45 AM, Joel S. Peiffer <[log in to unmask]>
> wrote:
>
> > William provides some good advice to derate the materials insulation
> > resistance significantly as well as providing some of the reasons
> > for doing this (copper surface roughness, dielectric defects).
> >
> > I would like to go into a little more detail on derating. The
> > boards operating conditions (temp, humidity) and expected service
> > life need to be taken into account as well. High temp/humidity
> > operating environments may call for additional derating. The
> > overlap area of high voltage should also be taken into
> > consideration. If the area is very small, the likelihood of a material defect is very small.
> > However, if the area is very large, the likelihood of a material
> > defect will increase in proportion to the area and the material may
> > have to be derated appropriately. Finally, the derating should be
> > dependent on the dielectric thickness. Thus, thicker materials need
> > to be derated less than thinner materials. For example, a 0.5 mil
> > defect may not have much impact on a 5 mil thick material but it
> > will have severe consequences on a
> > 1 mil thick material.
> >
> > If you need to utilize very thin dielectrics to ensure you meet you
> > z axis thickness requirements, you may want to look at materials
> > other than FR-4 to provide the required insulation resistance requirements.
> > Some of the polyimide film materials have excellent insulation
> > resistance and may be a better choice in this situation.
> >
> > Regards, Joel
> >
> >
> > Joel S. Peiffer
> > 3M Electronic Materials Solutions Division 3M Center, Building
> > 201-1E-17 St. Paul, MN 55144
> > Tel: (651) 575-1464
> > Cell: (612) 327-1983
> > [log in to unmask]
> >
> >
> >
> > From: "Brooks, William" <[log in to unmask]>
> > To: <[log in to unmask]>
> > Date: 06/20/2014 10:11 AM
> > Subject: Re: [DC] z-axis separation for high voltage
> > Sent by: DesignerCouncil <[log in to unmask]>
> >
> >
> >
> > The epoxy/glass dielectric actually is spec'd at 750V per mil
> > insulation resistance perpendicular to the layers according to
> > Mil-P-13949/4C for FR4 glass epoxy laminated materials. So 1.3 mils
> > minimum of material perpendicular to the layers would net you 1KV
> > insulation resistance top to bottom or internal layer to layer.
> >
> > Always give yourself some margin... The back side of the copper foil
> > is rough and can be 'spiked' on the laminated side for foil
> > adhesion... those spikes can cause the spacing to be less than the
> > minimum target spacing you require when laminated. Also there can be
> > bubbles or voids in the materials that could occur right between
> > your two high voltage conductors... Unless you are trying to mimic a
> > capacitance plane pair, there is little or no reason to have the
> > high
> voltage lines that close.
> > You don't want a short to occur internally in the board. Give
> > yourself a buffer of at least a couple of additional layers of 2 mil
> > prepreg on internal layers. Just saying... :) Good design practice
> > is to de-rate by 50%.
> >
> > I don't warranty sharing my observations... or advice... but if you
> > feel the need to compensate me... I like microbrewery beers... the
> > Darker Belgian style... I'm not a big hops lover... though I like
> > the hoppy beers too just not as much... :)
> >
> >
> > William Brooks, CID+
> > Senior MTS (Contract)
> > 2747 Loker Ave West
> > Carlsbad, CA 92010-6603
> > 760-930-7212
> > Fax: 760.918.8332
> > Mobile: 760.216.0170
> > E-mail: [log in to unmask]
> >
> >
> >
> > -----Original Message-----
> > From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
> > Jack Olson
> > Sent: Friday, June 20, 2014 7:35 AM
> > To: [log in to unmask]
> > Subject: [DC] z-axis separation for high voltage
> >
> > maybe I'm having a "not enough coffee yet" morning, but I was asked
> > how much separation I need between layers for high voltage.
> >
> > We have a design that may have 1700V in several places.
> > Since we are looking at a clearance into the board, layer-to-layer
> > I'm pretty sure I can use the "internal" column B1 of Table 6-1 in
> > IPC-2221 (using Table 6-1 for z-axis was discussed in a committee
> > meeting and no one
> > disagreed)
> >
> > but the number I get for 1700V is =
> > (.25 mm for the first 500V) plus (.0025 mm for each of the other
> > 1200V, 3
> > mm)
> > equals 3.25 mm
> >
> > For one thing, it already seems like I'm off-track because .25 for
> > 500V doesn't correspond very well with 3 mm for 1200V, but if you
> > can't trust IPC..... well, let's not go there.
> >
> > My REAL question is that, although I'm safe using 3.25 mm, my board
> > is not that thick!
> > Is there a smaller z-axis clearance that can be used for 1700V?
> > across typical FR4 material?
> > (we are using a RoHS compatible 170Tg /126)
> >
> > What's the MINIMUM layer spacing I can use for 1700V?
> >
> > thanks,
> > Jack
> >
> >
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