> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]] On 
> Behalf Of Scott Riley
> Sent: Tuesday, March 15, 2005 6:47 AM
> To: [log in to unmask]
> Subject: [DC] Schematics for high pin count BGA devices
> 
> I'm looking for a little information on the best way to represent BGA
> components with a high pin count (EX: 484 I/O) in a 
> schematic. I need to be
> able to document a schematic for a board that will have two 
> BGA devices (484
> I/O and 165 I/O). 

Scott,

On large pin count FPGA devices (we have gone up to 1120 and ~1500 is in
sight), we have found that partitioning by I/O voltage is appropriate.
These devices (Altera and Xilinx), have a separate voltage rail
associated with a group of I/O's and it is necessary to keep them
distinct, especially if you are using different logic levels for
different blocks.  What's more, many of the partitioned blocks use the
same schematic symbol, since they are partitioned as identical blocks in
the FPGA.  Then there will be one or two other blocks for the core
voltage, programming pins, etc.

Gary Crowell
Micron Technology

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