IPC-600 is correct, and here is something else to consider. Even if you have
a PWB that could not possibly come in contact with the cabinet or any other
conductive surface, the layers can still be shorted together due to copper
smears caused by routing, handling, etc. during fabrication and assembly.
This is true not only for the outer edges of the PWB, but for any non-plated
holes (Pemnut insertion, mounting hardware holes, cutouts, etc.).
So a good general rule of thumb is .050" etchback, minimum. For high power
or high frequency applications, you may even need more than that. And for
high-power, you want routed edges, not laser-cut. Laser-cut edges are OK for
low power applications, but because the laser cutting process can leave the
edges with a small amount of carbolization, this can lead to leakage from
one pin to the next, leading to more carbolization, more leakage, etc, until
catastrophic failure occurs.
I was recently called in to investigate a connector shorting issue. The
customer reported high-resistance shorting taking place "under the connector
insulator". They used an FR-4 insulator, and for years had never experienced
a short circuit on the connector soldering under the insulator (the
connector was wave soldered in place). Then all of a sudden they began
experiencing what they described as leakage currents in the area of the
connector. They suspected tin whiskers at first, because when they X-rayed
the connector there was no evidence of a short, and they assumed the solder
bridge or tin whisker "burnt away" when the power arced between the two
pins. The electrical shorting failures never occurred at test just prior to
shipping the product, it only happened to CCAs that were in the field for a
few weeks, perhaps even months later. When the failed CCAs were X-rayed, and
even when they were carefully cut off and the insulator lifted, there was no
indication of a solder bridge, only a charred spot on the insulator and on
the PWB surface.
There was a charred area on the topside of the PWB, but never on the bottom
of the PWB. Always on the bottom of the insulator, never on the top.
So they thought a possible voltage spike, and about 10,000 other things.
Well, to make a long story short, after about a week of investigation, I
looked at the insulator print. I noted that a change was made to go from a
routing process to a laser cutting process. The buyer had authorized this
change without any review, because the program manager decided there would
not be any risk involved (and wouldn't you or I assume the same thing?).
Then I took a good look at the insulators, and found that on the CCAs that
had the routed insulator, there were no failures. The failures did not begin
until about 3 weeks after the first shipment of laser cut insulators
arrived. The etchback on the PWB connector holes was just .020". This
allowed some current leakage through the PWB, up to the insulator, across to
the next hole in the insulator, and back down to the adjacent pins. After
awhile, you had so much current passing through the carbolized edges of the
insulator the card would fail while in service.
So, pay attention to details.
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of James
Jackson
Sent: Monday, June 03, 2013 12:48 PM
To: [log in to unmask]
Subject: Re: [DC] Exposed edge copper - internal planes
William,
This is exactly what I was looking for. I don't know how I missed finding it
- it's as plain as day - once I looked it up.
Thanks!!
Now... how does incoming inspection deal with this? IPC-600, I suppose...
Regards,
James Jackson
Oztronics
Quoting "Brooks, William" <[log in to unmask]>:
> IPC 2222 10.1.1 Edge Spacing - sets the requirement for MINIMUM edge
> spacing for conductors or spacing from non plated thru holes.
> It's a formula... .4mm (.016 in.) plus the required minimum voltage
> spacing requirements... you find those requirements by voltage range
> in IPC-2221 table 6-1.
>
> Rule of thumb for low voltage lines is about 20 to 25 mils for good
> laminating and some in there for process tolerances... Some folks go
> closer... but it can bite you if you aren't careful. Remember
tolerances...
> never, I repeat... never design to the minimums if you want to be
> successful. :)
>
>
>
>
> William Brooks, CID+
> Senior MTS (Contract)
> 2747 Loker Ave West
> Carlsbad, CA 92010-6603
> 760-930-7212
> Fax: 760.918.8332
> Mobile: 760.216.0170
> E-mail: [log in to unmask]
>
>
>
> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
> James Jackson
> Sent: Monday, June 03, 2013 10:07 AM
> To: [log in to unmask]
> Subject: [DC] Exposed edge copper - internal planes
>
> Is there an IPC callout for exposed edge copper?
>
> I seem to remember it not being allowed, but cannot locate an actual
> statement in any of the IPC documentation.
>
> What I am referring to is when you have a negative copper plane (or
> copper
> pour) on an internal layer that extends to the edge of the PCB. When
> it gets fabricated, there would be a small line of internal copper for
> each of the planes that extend to the edge of the PCB - which could be
> shorted together, if a metal object were brought into contact with the
> exposed copper.
>
> Any thoughts?
>
> Regards,
>
> James Jackson
> Oztronics
>
>
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