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June 2007

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Subject:
From:
Ted Tontis <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Wed, 6 Jun 2007 08:16:14 -0500
Content-Type:
text/plain
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text/plain (119 lines)
Bill,
    Altium offers the same option. Once you define the test point grid it
will change vias on that grid to test points. At least it did in DXP and
99SE, I haven't had an opportunity to try the new Altium Designer. I am
currently learning P-CAD 2000 and I place all my test points as components,
it is very time consuming. I have been trying to talk my new employer into
upgrading to the new Altium Designer.

Regards,

Ted
----- Original Message ----- 
From: "Karl Bates" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, June 06, 2007 6:47 AM
Subject: Re: [DC] ICT, bed-of-nails and CAD tool support?


> Bill,
> I use Mentor Expedition, and Cadence Allegro.    In Expedition, I run the
> testpoint program and choose from a list of items that I can add a
testpoint
> over (vias, pins, traces etc.)    and it adds a testpoint with the rules I
> have selected.   I typically try to fanout all SMT devices to a via, as it
> helps
> achieve full testability and also adds a point to add a wire to if someone
> makes a "improvement".
> The output file that is used by the testing house is "Mitron Gencad".
> For Cadence the higher tier tool (Performance option) has the testpoint
> ability, as I only  have the lower tier PCB Editor I do my best to add
vias
> spaced nicely with larger probable pads on the bottom side.    I do not
> output anything special with this.
> Karl
>
>
> From: "Brooks,Bill" <[log in to unmask]>
> Reply-To: "(Designers Council Forum)" <[log in to unmask]>,
>   "Brooks,Bill" <[log in to unmask]>
> To: [log in to unmask]
> Subject: [DC] ICT, bed-of-nails and CAD tool support?
> Date: Tue, 5 Jun 2007 17:15:38 -0700
>
> 'In-Circuit Test' is a seldom discussed subject at the 'designer's round
> table' here...
>
>
>
> I'm curious how other designers are affected by test points and how they
> deal with testability in their designs.
>
>
>
> I have placed test points in schematics and treated them as 'components'
on
> the board before...
>
> What have you seen for test point support from the CAD vendors and is
there
> an easy way to automate this?
>
> Also those who have to test for a living... what is the process you use
and
> are the outputs from these CAD tools any help?
>
>
>
>
>
> Best regards,
>
>
>
> Bill Brooks, CID+
>
>
>
>
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