Hi Matthew,
In fact, the comment that the caps are 2mm from the board edge and that they
are using a depaneling tool makes it 'Highly Likely' that the caps are being
BROKEN... in depanelization. Are you Vee-scoring the panels? If so, the
flexing at the vscore edge may be the culprit... at least it is the first
place I would really look closely at. I have seen app notes on just that
exact scenario where ceramic caps were failing due to the induced flexural
stress inherent in depanelization. Are the ones that crack near the edge and
at right angles to the edge? Or parallel? This is a very plausible cause...
Let me know what you find.
Re: pad sizes, I think the larger the land area the more heat it will
conduct to the solderpaste. If they are unduly small it will take a higher
temp to melt the solder in the same amount of time (or they need to slow the
machine to soak the board longer in to achieve melting temp) and there will
be very little fillet, (the thing that give the component it's mechanical
strength.) Too large will require a greater amount of paste and wasted
solder paste occurs... and parts float from one side to the other or
tombstone (stand up vertically) if unevenly flowed.. The IPC tries to give
min max values and not a 'recommended size' That's what the designer is
supposed to figure out... (although in practice many use the minimum
values.) Many designers use different pad sizes and rules for wave solder vs
IR reflow vs vapor phase soldering... there are many methods... the trick is
to design it for the manufacturing process most likely to be used.
- Bill Brooks
Bill Brooks
PCB Design Engineer , C.I.D.
DATRON WORLD COMMUNICATIONS, INC
3030 Enterprise Court
Vista, CA 92083
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
mailto:[log in to unmask]
IPC Designers Council, San Diego Chapter
http://www.ipc.org/SanDiego/
http://home.fda.net/bbrooks/pca/pca.htm
-----Original Message-----
From: Matthew Lamkin
[mailto:[log in to unmask]]
Sent: Tuesday, August 28, 2001 4:36 AM
To: '(Designers Council Forum)'; 'Brooks,Bill'
Subject: RE: [DC] Capacitor pad reduction ?
Hello Bill, thanks for that reply and no it was not too much information.
In fact, the more the better.
Thermal shock to the caps could be the cause of the problem as we don't
actually know
what's doing it.
We have a small board, that has some 0805 ceramic caps on, and on some about
10
from a batch of 200 failed on site.
The tests showed that it was the caps that were at fault.
Although I have oodles of information that points to many areas of the
production of these boards, the
rumbles that I am hearing are that they want us to try a different/thinner
pad and further away from the board
edge (currently 2mm). We have a thought that it could be when they are
depanelled through the pizza cutter.
Although this board has been made for several years with thousand that are
OK, a slight batch/process fault
resulted in the proverbial hitting the fan and "it must be a bad design"
comments.
Now I don't mind changing the design to keep them happy, I have no
objections to reducing the width of the pads
on ceramic capacitors, however I do insist on it being correct when its done
though.
I can tell from measuring them, that different value ceramic caps have
different dimensions despite
having an "0805" generic package. This points to needing different pad sizes
per component value
if a specific amount of reduction is going to apply. Also I have documents
that say that the reduced pad width
is for Wave soldering and does not mention Reflow. This makes me question if
it applies to Convection Reflow
soldering at all?
If I make the pads narrower than the component then I ask what length should
they be, distance between the pads
and what shape...
The whole issue is a minefield of both technical information and political
issues & its doing my head in...... :-/
Matthew Lamkin
AKA "Confused of Lancashire, UK."
> -----Original Message-----
> From: Brooks,Bill [SMTP:[log in to unmask]]
> Sent: Monday, August 27, 2001 4:43 PM
> To: [log in to unmask]
> Subject: Re: [DC] Capacitor pad reduction ?
>
> Mario,
>
> Ceramic Capacitors are made up of a 'layer cake' of palladium laden inks
> and thin sheets of green ceramic material that has been heat dried to
> remove
> the binders in the inks and pressed together with about 1200 lb hydraulic
> press. Then cut and fired in a kiln and dipped silvered ends.... (I know
> far
> too much about this process... I worked for a ceramic capacitor
> manufacturer
> before). If this process is not controlled well you can create embedded
> stresses in the materials and the caps will tend to crack along the
> layers...
> When you Solder these to a PCB you heat the board and the caps, causing
> them to expand in size, unevenly. The rate at which they are heated
> affects
> the difference in their sizes over time... hence the amount of induced
> stress applied to the caps. As they cool, the ceramic is captured in the
> solidified solder and has added a stress to the cap due to the uneven
> coefficient of thermal expansion of the board and the cap. If the caps are
> being temp cycled, rapidly, (in manufacturing or in the field), this can
> cause a severe delta (difference in change) in the physical size of the
> cap
> and the land it has been attached to. This induced stress can cause
> fractures to develop in the layers of the caps as well. When you get a bad
> batch of ceramic caps...(with captured stresses embedded in them or
> weakness
> in their bonds between layers) it's hard to tell if the caps are a fault
> or
> the process is at fault but the problem is magnified.
> One of the things a designer can do is change the material of the board to
> a
> more stable material with a better TCE. (Remember this is also a cost
> driver) Also the EE and the ME can look at the specs for the caps and
> specify that they survive under the conditions to which they have been
> applied.... both environmentally and in manufacturing processes... They
> may
> be able to reduce the failures by controlling the rate of the ramp up and
> down of the temperatures that the assembly is being exposed to. Better
> rated
> caps can also have an affect on the cracking. Also check to see that the
> board is not being flexed in excess... this can create mechanical fatigue
> of
> the caps and their solder joints...
>
> Sorry if that was too much info... I didn't know the conditions under
> which
> the failure was occurring, so you get the ones I can think of, off the top
> of my head..
> The least likely cause is pad geometry if you are using the IPC land
> pattern
> guides... I have had terrific success with those geometries... and they
> are
> fairly tolerant of deviations... More or less fillet on the side of the
> cap
> will affect the flexural survival of the fillet... but I doubt it will
> have
> much to do with cracking of the caps in general.
>
>
> Good Luck - Bill
>
> Bill Brooks
> PCB Design Engineer , CID
> DATRON WORLD COMMUNICATIONS, INC <http://www.dtsi.com/>.
> 3030 Enterprise Court
> Vista, CA 92083
> Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
> mailto:[log in to unmask]
> IPC Designers Council, San Diego Chapter
> http://www.ipc.org/SanDiego/
> http://home.fda.net/bbrooks/pca/pca.htm
>
>
>
> -----Original Message-----
> From: Mario Irigoyen [mailto:[log in to unmask]]
> Sent: Monday, August 27, 2001 7:42 AM
> To: [log in to unmask]
> Subject: Re: [DC] Capacitor pad reduction ?
>
>
> Hi,
>
> My suggestion would be to run some tests. Create at least 4 different
> configurations (pad geometries) for each component type and place about of
> 100 of each on a test board. Run at least 10 boards through manufacturing
> and do a quantitative analysis to determine which geometry(s) produce the
> fewest defects. Then no one can argue "whose fault".
>
> Best regards,
>
> Mario Irigoyen
>
> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]]On Behalf Of
> Matthew Lamkin
> Sent: Monday, August 27, 2001 9:09 AM
> To: [log in to unmask]
> Subject: [DC] Capacitor pad reduction ?
>
>
> Hello everyone,
> I wonder if I can tap into your experience of cracking of ceramic
> capacitors.
>
> I have a situation where the shop floor are having problems with cracked
> capacitors, due to
> several possible causes.
> However, the blame for the problem is being thrown at design with an
> instruction to reduce
> the width of the pads (1206/0805/0603 caps only) to be less than the width
> of the component.
>
> Now there are many documents out there advocating using the IPC SM-782-A
> pads, and many that
> advocate reducing the pads.
> However, I have the IPC specs which give me actual dimensions to follow
> whereas the documents
> that advocate reduced pad widths do not.
>
> Can anyone give me some advice on what size these pads should be when
> reduced to prevent MLCC cracking?
>
> Can anyone supply a URL of a document that gives any good information on
> this?
>
> I have many documents from AVX/SYFER etc on the subject but they do not
> quote any figures on reducing the width.
>
> Thankyou -
> Matthew Lamkin
> Protec Fire Detection PLC.
> England, U.K., Planet Earth.
>
> P.S. Come on Steve, I'm timing you now, to see how long it takes until you
> quote a website....he, he....
>
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