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September 2015

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Subject:
From:
"Jenkins, Jeffrey A @ CSG - LINKABIT" <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Thu, 24 Sep 2015 22:05:09 +0000
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Jose,

I think if you factored a 50% increase over the design time you'd be good.  What really will drive this is the annular rings of the vias, what they impact, and how they impact your escape channels from dense devices (e.g. BGAs).
This may require additional layers for escape than what you'd need otherwise.  Other gotchas are if you're doing seq-lams as they can increase your Cu due to additional plating cycles on external traces which may cause you a redesign.

If you plan it out before the layout, really it won't be much more than a class 2 board, more like 15-25%.  But if you are taking a class 2 board to class 3 (e.g. up design), it's going to be bit of a project.

I'd also recommend that before you send to fab, you have your favorite board house run a check on the design to make sure your annular rings and other Cu features can be processed to the Class 3A.  They may take a day to do so and a day or two for you to revise the design.  But that is far better than the fab house coming back and saying they can't build a class 3A board to your design due to annular rings or that the external plating will cause spacing issues.  

Work with them on the final vias and external traces and get your stack up dialed in beforehand.  It'll save you a lot of headache.

Best,
-Jeffrey

Jeffrey A. Jenkins
Sr. PCB Staff Designer, CID+/CIT
L-3 Communications, Linkabit Division
Work:  858-552-9832
Email:  [log in to unmask]

 

-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Jose A Rios
Sent: Thursday, September 24, 2015 2:53 PM
To: [log in to unmask]
Subject: Re: [DC] Class 3 vs 3/A layout; is there a difference??

Hi William, I’m in agreement with what you’re saying when going from Class 2 to 3. What I meant to ask is if you go from Class 2 to say 3/A, would that double the time to do layout relative to going from Class 2 to 3 ??? Outside of updating fab notes in a drawing I’m mostly asking in regards to re-routing traces and actual layout effort. Thanks,

> On Sep 24, 2015, at 5:31 PM, Brooks, William <[log in to unmask]> wrote:
> 
> My guess is that anything that is outside the norm is typically a time/cost factor. 
> For example, the templates that we use to save time are typically for class 2 boards... If we needed to build to class 3 there would be time spent up-dating the notes to class 3... each detail that deviates from standard, become a 'custom thing'... requiring time to develop a correct feature, notes, tables, etc and more checking time... so I would guess it would take most shops more time. If it's 'run of the mill' normal, then all of the work has already been done in the documentation templates... etc. which allows less time or the fastest time to get the job done. 
> 
> Other things that can affect the time to get the job done are troubles like being restricted in via pad geometries to larger sizes that make the board harder to route. Wider spaces between traces, or thicker trace widths... etc. 
> 
> Does that help?
> 
> 
> 
> William Brooks, CID+
> Printed Circuit Designer
> 2747 Loker Ave West
> Carlsbad, CA 92010-6603
> 760-930-7212
> Fax:        760.918.8332
> Mobile:    760.216.0170
> E-mail:    [log in to unmask]
> 
> 
> 
> 
> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of 
> Jose A Rios
> Sent: Thursday, September 24, 2015 8:42 AM
> To: [log in to unmask]
> Subject: [DC] Class 3 vs 3/A layout; is there a difference??
> 
> For board design/layout, should one expect a significant increase in required layout lead times when specifying fabrication to 6012C Class 3/A, as opposed to Class 3 ?? I can understand that a layout to Class 3 would take longer to obtain, over the same board laid out to Class 2; but from 3 to 3/A should one expect an order of magnitude increase in the time it takes to do a layout ??? What about 6012B (which has a 2 mil min internal annular ring requirement for 3/A) ??  I’m thinking not, but I just want to validate that.
> 
> José (Joey) Ríos, Sr QA Engineer
> Mission Assurance
> Kavli Institute for Astrophysics & Space Research Massachusetts 
> Institute of Technology [log in to unmask]<mailto:[log in to unmask]>
> (617)324-6272
> 
> 
> 
> 
> 
> 
> 
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