Whew, that is a lot of issues to address in one email!
I think some of the confusion may be related to terminology.
I'm "home alone" tonight, so I'll attempt an answer but since I don't have specs anything I say will be from memory. Anyone PLEASE correct me if I say anything misleading or inaccurate, ok?

I don't think the IPC makes a distiction between plated via holes and plated component mounting holes in any way that would help us with this subject. The only real difference would be the finished hole TOLERANCE, (which is less important for vias anyway) but that's not related to the question "How do you figure the minimum via hole/land sizes for a particular design that meets IPC guidelines?"

Your comments about soldering are valid but not in how a minimum land size is calculated. You could say that a land size should be INCREASED for assembly/soldering/rework reasons, and you could say the hole diamter needs to be INCREASED to accomodate a current requirement, but neither of these are a factor for how to calculate the MIMIMUM land size for a particular hole size. That is defined only by the MAXIMUM DRILL, the MINIMUM ANNULAR RING, and the FABRICATION TOLERANCE. (Section 9.1 in the design guideline I think)

The first term (MAXIMUM DRILL) is related to your statement about "MFG drill-to-thickness tolerance" being 10%. Does this correspond to the terminology IPC uses when it refers to "aspect ratio"?. If so, I believe you should take a second look at this. From my experience a 10:1 aspect ratio is not preferred, and I believe the IPC would recommend about half that. We are drilling .013 holes in .093 which is already not standard (7:1), and if we tried to change it to 9 (for a 10:1 ratio) our vendors would scream. Definitely not IPC recommended, in any case.
In addition to aspect ratio, there is also Table 9-6 in IPC-2222 which recommends different minimum via sizes (drills) for different thicknesses of different Class boards. This is much more specific than a general aspect ratio, so it deserves some attention. (and I haven't calculated the range of aspect ratios for all the numbers in the Table, I think I'll save that for a rainy day... grin)

The second term (ANNULAR RING) is easy to misinterpret. If someone says "we add 12 mils to the hole size to get a 6 mil annular ring" it means a different thing than the way we have to use MINIMUM annular ring in an IPC calculation. The minimum annular ring we would accept is 1 mil. This means that since fabrication processes aren't totally accurate, chances are you will NEVER have a hole drilled directly in the center of the pad. But how far off center can it be? Well, assume that the design will still be reliable even if the edge of the drill is only 1mil away from the edge of the pad. Will it still work? What if it crosses the edge of the pad, the minimum annular is now 0 and the pad is cut into a moon shape. This is called breakout and could separate a trace from the via to create an open circuit. It would be avoided by specifying a 1mil MINIMUM (that's as far as I want to explain, some people may argue for a LARGER minimum annular ring, but let's not get off track)

The last term (FABRICATION TOLERANCE) is the key to the whole puzzle. We know the size hole we need for good plating, we know we need at least one mil of copper between the drill and the ege of the pad. Imagine that your fabrication is perfect in every way, and never misregisters anything and drills every hole the perfect size in the center of every pad. If so, you could declare a tolerance of ZERO (who needs a tolerance?) and your minimum pad size would be your maximum drill plus two minimum annular ring, or 2mils. And yes, in a perfect world this would probably work just fine. But back to reality, how do you determine the amount of slop you are going to allow? You could add up every way a board could go wrong, and end up with a tolerance of about 40mils? No, there is some way they use a statistical "sum of the squares" or something to get a "reasonable" value but let's not go there. The slop you can handle is directly tied to the producibility level you want (Level A, B or C!
!
) and to the maximum length of the board, and also you are supposed to add a little extra if it is more than 8 layers. There is a Table for this too, I think in the same section of IPC-2221 (9.1?)

Once you have the fabrication tolerance that fits most of your designs (proabably in the 8-12mil range), the calculation is simple: MIMIMUMLAND=DRILL+TOLERANCE+2RINGS


Lastly, I want to say something about your method of determining pad sizes in the section of your mail called "These are my findings". I don't want to sound too critical by attacking your method, so I should start off by saying it is my PERSONAL design philosophy that as the IPC guidelines become more and more prevalent/studied/understood, it is in my best interest to TRY to use them. If I can possibly find a way to make them work it provides a level of consistency and reliability that I will never have to defend. A vendor that has a problem with a design that meets IPC design guidelines doesn't really have a leg to stand on, in my opinion. However, there are times when a rule will need to be broken, and I would want to know WHY I am breaking it and be able to provide a reason for breaking it if anyone asks, which only works if I understand the principle behind it.
But again, that is just my PERSONAL design philosophy.

So with that in mind, when I see your formulas for pad sizes and I can't see any way to correlate your result with IPC recommended results, and I can't see any underlying principle for doing it that way, and you don't supply a reason for modifying the published formula that would show an improvement or innovation, then it is very difficuclt to discuss it in any rational way. That is why I always push people (sometimes with not-so-pleasant results) to please START with IPC so we all have a foundation to build on, and then explain why you are veering away from it, so everyone at least has the ability to "get up to speed" if they are in a similar situation. (oops, there's more philosophy again, sorry...) I know you said "the percent accomodates a larger lead that requires more heat thus requiring a larger pad" but I don't have enough experience in that area to know what it means.

-=-=-

I'm not usually so verbose, but I admire your efforts to share what you have learned with all of us.
and Thanks for the spreadsheet, it has given me an idea for how to rapidly make design decisions for "weird stuff" (yet another rainy day project, eh?)

onward thru the fog,
Jack

-----Original Message-----
From: Chris Robertson [mailto:[log in to unmask]]
Sent: Thursday, April 26, 2001 7:26 AM
To: 'DesignerCouncil E-Mail Forum.'; Olson, Jack
Subject: RE: [DC] Minimum Via Size for .093 Thick PCB


Jack,
I'm not arguing this issue, just trying to understand.

From what I've read general vias are in the same category
as through hole in general...Plate thru-holes.

The blind and buried vias are the only ones that have a description as to
the thickness of the material.

There are several problem/questions I find here. First there isn't a
delineation between soldered pads and unsoldered pads. This is most of the
reasons for land diameter. The difference is whether the pad will be
soldered or not, is it not? Vias are normal not soldered (same as blind and
buried vias) I also don't understand why there is a specification, at all
for b&b vias per thickness. I would believe that this is between you and
your manufacturer. As a guideline I could understand.
Also the issue of annular ring at all, for vias really should be controlled
by the technology, current capacity and guidelines for annular ring over the
hole diameter.
Currently if we had no MFG tolerance to add to the AR then the finished pad
could be less than the hole plating (.005 plating)? That doesn't seem quite
right. Shouldn't both the external and internal pads be defined from the
drilled hole?

I believe this is why most of us say, "this is what IPC says, but this is
what we do".

These are my findings:
Formula for External (soldered) pad
        Drilled hole x 15% + MFG tolerance
Formula for Internal pad/via
        Drilled hole x 10% + MFG tolerance
Formula for External (unsoldered) pad (via)
        Drilled hole x 10% + MFG tolerance


The percent accommodates a larger lead that requires more heat thus
requiring a larger pad.

As for MFG drill-to-thickness tolerance, I believe its around 10%
(example .125 * 10% = .0125" drilled /.008 finished)
I get .125" board with .008"(finished) holes...

Personally I use much larger pads, but this would be a good minimum.
I attached a spreadsheet calculator for your review.

Chris Robertson
[log in to unmask]
<mailto:[log in to unmask]>

Senior Designer
Lockheed-Martin Services Inc.
4912 Research Dr.
Huntsville, AL 35805
(256) 722-2626







Yes, it was a rather silly question to ask -
"Can anyone think of a way to design PCBs to meet IPC with a smaller via?"
because if you say you design to IPC, you have to use the numbers, right?

It is interesting that most all of the answers I got (thanks everyone!)
said something like "yes, the IPC says xxx but we do this..."
and in most cases it seems that although people know what it says,
they go on and do it their own way anyway.

I purposely picked our worst case (over12",>8lyr) to see if anyone had
creative comments, but for anyone reading along looking for answers...

I would probably compromise by designing a via for:
settling for Class 1, which drops the minimum drill size to 15.74 mils
assume less than 12" length typical, which drops the fab tolerance to 9.84
This changes the whole equation to give a via hole 16 with pad 28

I think I could actually design a board with a 16/28 via, eh?

(and for those of you who recommended a 2mil annular ring or an 18/30 via
I'm not arguing your point, that works for me too)

Anyway, thanks again for all the responses, both public and private!

onward through the fog,
Jack, the new guy


-----Original Message-----
From: Ledwinka, Mike [mailto:[log in to unmask]]
Sent: Wednesday, April 25, 2001 7:11 AM
To: The PCD List
Subject: [pcdlist] RE: Minimum Via Size for .093 Thick PCB


Jack,

I see your logic entirely ( rather IPC's) in their quest to be the authority
on PCB standards and the like.  These days I haven't used 20 mil via for
routing unless the tracks where carrying high current.  And with regard to
that "monster" flash on the drill, I can only chuckle at the difficulties I
would encounter.  I tend to use IPC as a ballpark figure or as a basis for
the direction in which I should head when encountering unfamiliar territory.
Seeing the last board I did was 22 layers ( 93 mil thick ), with a 12 mil
drill for bga's and a 13 mil drill for vias.  The only reason I used a flash
of 35 mils on the vias was to accommodate probe testing. Its just my
opinion.

Mike Ledwinka

Any replies to this message by previous employers/co-workers is deemed an
attack on my character :)


-----Original Message-----
From:   Olson, Jack
Sent:   Tuesday, April 24, 2001 4:44 PM
To:     DesignerCouncil (E-mail); PCDLIST (E-mail)
Subject:        Minimum Via Size for .093 Thick PCB

As a result of some discussion with our in-house manufacturing,
we decided to re-evaluate our minimum via size for .093 board thickness.
Just for fun (grin) I decided to look everything up in the latest IPC specs.

If anyone enjoys poking holes in IPC logic, here is the result:
(see below for supporting references)

calculated IPC minimum via size = 19.7 mil drill with 41.4 mil land

Can anyone think of a way to design PCBs to meet IPC with a smaller via?

-=-=-

Our initial parameters are:
Design for Class 2 (no one is going to die if the product fails)
Assume Level C producibility but prefer Level B (ha!)
Many designs are >12" long
Many designs are >8 layers

According to IPC-2222 Table 9-6,
a plated through via on a board >2mm thick for Class 2  is .5mm minimum
Result: the minimum drill size is 19.68mils

According to IPC-2221 Table 9-1,
For a Level C board up to 450mm dimension (<18inches)
and with note 2 to add .05mm to .45mm for >8 layers is .5mm minimum
Result: Minimum Fabrication Tolerance is 19.68mils

According to IPC-2222 Paragraph 9.1.1
minimum land = a + 2b + c
where
a = maximum drill diameter (19.68mils)
b = minimum annular ring (1mil)
c = fabrication allowance (19.68mils)
Result: minimum land diameter is 41.37mils

A 20 mil hole with a 42 mil pad is difficult to design with.
To meet IPC even at Level C, the only thing I can see to reduce is
the minimum annular ring to allow breakout, are ya kiddin me?
Am I missing something?

Any comments are greatly appreciated!

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