Hi Jack-
We have the vias filled with solder mask and covered (not ‘TENTED’). We’re not paying for a secondary process. Some vias will either not get fully filled, or will open during reflow. So as others have also commented, vias will allow solder to wick during the wave process; the glue stops that from happening. The only added cost we have is for extra glue.
Kitty
From: Jack Olson [mailto:[log in to unmask]]
Sent: Monday, December 19, 2016 8:34 AM
To: (Designers Council Forum) <[log in to unmask]>; Hines, Kitty <[log in to unmask]>
Subject: Re: [DC] Plugging Thermal Via Holes with Soldermask?
Hi Kitty,
thanks for the interesting idea! I have never heard of that.
We don't use wave soldering anymore, so we have cut the "adhesive" process out of the equation,
What I don't understand is why you add adhesive dots on those vias if they are already filled and tented?
(I could see using that method to AVOID the filling process)
just curious,
Jack
On Thu, Dec 15, 2016 at 1:55 PM, Hines, Kitty <[log in to unmask]<mailto:[log in to unmask]>> wrote:
Hi Jack,
We have been struggling with the same problem. We started adding a geometry to the glue stencil that will allow the glue to cover those bottom side vias. The boards go thru reflow without wicking any solder thru. The Fab drawing also calls out those vias to be "FULLY FILLED AND COVERED WITH SOLDER MASK ON SINGLE-SIDE ONLY (BOTTOM) PER IPC-4761, TYPE VI (a)." Any solder balls in the hole will melt in the reflow ovens, and the glue stops solder from wicking up during the solder wave process. So far, this has been working for us. Do you see problems with this method?
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]<mailto:[log in to unmask]>] On Behalf Of Jack Olson
Sent: Thursday, December 15, 2016 10:10 AM
To: [log in to unmask]<mailto:[log in to unmask]>
Subject: [DC] Plugging Thermal Via Holes with Soldermask?
I'm looking at the various options for tenting/plugging/capping vias in
IPC-4761 (Via Protection Guidelines). None of the options seem to address the thermal vias in power pads.
We are trying to:
1) have a solderable pad, apply paste on that side (of course)
2) prevent solder from creating bumps on the heatsink side (of course)
3) avoid the cost of plugging/capping
IPC-4671 states that all forms of one-sided via protection are NOT RECOMMENDED.
So here's the question - I know I have seen a picture of a thermal pad in an IPC document where I could see vias with green mask material in them on the paste side (the component side), but the green stuff was only in the holes, which left the thermal pad exposed for soldering.
I don't think this would be called TENTING because there's no mask on the pad. but is this an acceptable practice? Can I instruct a bare board fabricator to put mask in holes from the top side, but keep the pad clear?
(I can't remember where I saw the picture!)
If that's NOT an accepted practice, is there a way to design the hole big enough to plate but small enough to prevent solder flowing through the other side of the board? I couldn't find a discussion of that in the TechNet Archives
thanks,
Jack
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