*Currently our PCB designs utilize "encroached" solder mask via pads on
pin escapes for all of our products. 
This was an adequate treatment for products with 1.27mm but as BGA lead
pitch starts shrinking, the issue of adequate solder dams between ball
pads and their pin escape vias  becomes more problematic. 
Our standard pin escape via pad is typically .024" with .012" Finished
Hole Size (FHS). Our requirement is solder mask encroached 1:1 with FHS.
*First dilemma is that fabricators require .006" solder mask clearance
over primary drill size. 
*This yields .001" solder mask encroachment on a .024" via pad with a
.012" FHS under ideal conditions with no mask misregistration. 
*Problem becomes more pronounced with .8mm BGA pin escape vias. Our
typical pad geometry for .8mm BGAs is .016". The pin escape via pad
diameter for these devices is typically .018". That will yield only
.005" clearance  between the via pad and adjacent BGA pad. If fabricator
requests .006" over primary drill, that leaves 0 solder mask on pin
escape via pad with perfect solder mask registration. Problem is further
exacerbated when fabricators increase solder mask apertures to
accommodate misregistration and prevent solder mask from getting onto
SMT pads. This results in as little as .003" solder dams. 
*Predict that there will be an abundance of issues whenever parts need
to be reworked. 
 Our preferred PCB surface finish is ENIG with SMOBC construction. 
*Typical practice in industry is to "tent" over vias with LPI. However,
this practice is problematic and can lead to long-term PCB reliability
issues. 
*Tenting vias with LPI solder mask will cause ENIG plating chemistry to
become entrapped in vias. 
I would like to know how others are handling vias under BGA's with a
pitch of .8mm or less.
 
If we plug our vias we will have the following issues:

*	
	Via fill process will increase cost of PCB and will potentially
increase lead time as well. 
*	
	*Need to have vias covered with solder mask on BGA placement
side to prevent potential for solder wicking onto via land. This becomes
very critical during rework operations. 
	
*	
	*Need to have vias exposed on non-placement side for test
access. 
	
*	
	*Vias filled with non-conductive media will cause probe contact
issues during flying probe and In-circuit test. 

*
Any help would be appreciated
 
Stephen J. Mariani
Mercury Computer Systems, Inc.
199 Riverneck Road
Chelmsford, MA 01824
Phone: 978-967-1855
Cell Phone: 978-761-4101
Fax: 978-244-0520
Email: [log in to unmask]
 
 

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