At 08:39 AM 6/21/96 -0700, Mitch S. Morey wrote:
>Hi Fred,
>
>Good questions, I hope you will be able to post the responses you get aside
>from responses through the designer's council (like this one). I've been in
>the pcb design phase for about 15 years, so I've seen way too much of what goes
>on.
>
>> Has anybody been using SMT Plus land patterns? They are advertising a lib.
>> for P-Cad. How do they compare to the IPC 782 Patterns?
>>
>Here at TRW we have implimented the SMT Plus footprints as our standard. When
>I first saw the pre-draft of 782A I about croaked. It's no longer a design
>standard, it's only a guide (as it implies) and MUST be tailored to your own
>practices (fab and assembly issues). We could use it as a standard before the
>Rev A as it wasn't a "left-field" all incompassing document.
> 

Mitch;

The comment heard most often, involving the original IPC-SM-782, was that it
was difficult to tailor to one's specific process. The users asked for a
standard that would provide sufficient information to apply the land pattern
principles to newly released components, as well as customize the land
pattern for their own processes. In addition, they questioned the fact that
we did not provide an input for machine accuracy or fabrication tolerances. 

When the committee drafted the 782A, they took these wishes into
consideration. The result is a standard that provides information on the
principles of land pattern creation, as well as what variables our peers
recommended to be used in the calculations.

As with the original 782, if one did not wish to make calculations, they
would simply use the values in the tables. If you were energetic and wished
to customize or create a new land pattern, then you had the formulas to work
with. The IPC supplemented the 782A with an electronic version. This
electronic spreadsheet simplifies the creation of new land patterns. One
would input the component size and tolerances, assembly accuracy,
fabrication tolerances, and desired solder fillet information. The land
pattern would be created with immediate feedback concerning your solder
fillet goals. The designer can then modify some of his numbers to achieve
fillet and/or land pattern goals. If the designer did not wish to create new
variables, he simply used the default values from the standard table.

I would hate for any standard to force anyone to be creative, let alone
prematurely croak. 


>> What are you doing as far as via's and conductors under SMD components? I
>> noticed the P-Cad lib has keepouts under the chip components. I have been
>> routing traces under SMD and have not had any problems.
>>
>Hasn't been a problem with us. 'Course we are not military, and that seems to
>be the only case I can think that requires this. It's mostly a concern for
>reliability, and whether the pcb is clean under the SMD.
> 
>> Has anyone needed to provide a glue dot file for mfg? I noticed that P-Cad
>> has that capability but I have never had to provide one in the past. It was
>> always created from the placement file.
>>
>Glue dots are fine, provided it's what your assy house can use and will use.
>We don't provide it, because it's really too hard to stay abreast of what our
>many assy houses can and can't do, or can do faster with more data. But, that's
>not to say if you work with one assy house you couldn't provide them this.
> 
>> Silk Screen legend sizes seem to be very large on most commercial lib's
>> compared to what I have been using. I seem to get away with .008 width and
>> sometimes down to .060 height. What is your experience?
>>
>Remember, first and foremost, the design lib (like 782A) will first need to be
>tailored to suit your needs and requirements BEFORE you use them. .008s and 
>.060 hts have worked fine for us. As long as you keep in mind what line widths
>you use compared with heights you won't get anything you can't read.
>
>> board is finished now but I just know placing the parts for optimal routing
>> would have resulted in much shorter runs, and a more functional layout. What
>> is your opinion? How are you doing it?
>>
>TTL boards, this is desireable. For high-speed ECl/MECL boards this practice
>will go the wayside. Function will be more important. I don't personally care
>for "optimal" placement because it doesn't save me a dime with pick&place. What
>does is the type(s) of components you use (dip, SMT or dip/SMT) and placement
>design issues (have you considered all mfg requirements and practices?, spacing
>reqmts, fine pitch, fiducials, tooling holes, etc.)
> 
>> I also was prohibited from putting chip caps on the solder side, even though
>> I routinely do it with other designs. Are any of you designing boards that
>> are waved with chip caps on the solder side?
>> 
>Chip caps up to and including 1206 size are ok for wave side for our practices,
>and we don't put active comps on the wave side, BUT look at commerical boards.
>They do most anything. My practice is, if you use a good assy house, they will
>do your boards as best as they can to get you the best board possible. If they
>feel they can't acheive good solderability with wave on the back side, they
>will IR reflow or vapor phase both sides. Done.
>
>It's best to know what your fab and assy houses can and can't do for you, what
>input they need from you and how you can tailor that to your requirements.
>Enough said.
>
>Good Luck,
>Mitch Morey
>Sr. PCB Designer
>TRW, Inc.
>Redondo Beach, CA 90278
>Phone: (310)814-5765
>Fax:   (310)812-4949
>EMAIL: [log in to unmask]
>
>                               |||||
>                              ((o o))
>____________________________oOO_(_)_OOo_____________________________
>
>     PCB layout is like fine art. You have to DIE to be famous!
>____________________________________________________________________
>                             (_)   (_)
>
>
Regards,

Gary Ferrari
Tech Circuits
(203)269-3311
[log in to unmask]