Actually, Dr. Charles W. Jennings conducted the research at Sandia National Labs, and presented it in his paper "Electrical Properties of Printed Wiring Boards" at the IPC Fall Meeting in September 1976.
The paper is IPC-TP-117 and is available from the IPC Order department ($10 for IPC members; $20 for nonmembers).
Mike Buetow
IPC Staff
>>> Jack Olson <[log in to unmask]> 09/15/97 11:15AM >>>
speedy turtle wrote:
> Since the IPC and it's members can' validate this data or produce
> formulas to validate it. How can it be trusted or published ?
> How about doing a new study ?
BACKGROUND INFO FROM PREVIOUS DISCUSSION OF THIS TOPIC
Maybe somebody at IPC HQ can corroborate this but I've long been
under the impression that the venerable IPC-D-275 current handling
charts, which came from the Mil standard of the same number, was
generated not from a mathematical formula, but from plotting
measured temperature rise vs current data on the different widths
and weights of traces. Can anybody out there support or refute
this statement?
AMP has in isolated instances tried to duplicate these measurments
and quickly came to the conclusion that "2 OZ copper thickness"
statements don't guarantee a well controlled conductor thickness.
To do justice to this type of measurement, one would have to
verify every test panel as to copper thickness and trace width,
such that an accurate cross-section of each tested conductor could
be documented. Definitely tedious. If you didn't, you'd have to
design a test which included a relativley large sample population
to ensure that a "nominal" copper weight and trace width were
being used for each measured situation of each variable. VERY
tedious. Hence people like myself fall back on the "official"
table in IPC-D-275. And that works for most situations.
If that chart WAS generated by a formula, I'd think some of us
would like to know that some empirical data was measured and
analyzed to verify said formula. I'd like to know how or if that
was ever done.
Leonard F. Bendiksen
AMP Incorporated
Test Engineer and
PCB/Fixture Designer
Americas Regional Laboratories
[log in to unmask]
(717)780-6493
-=x=-
From: Mike Buetow <[log in to unmask]>
The charts in IPC-D-275 are based on research conducted by Charles
Jannings at Sandia National Labs.
Jannings' report describes a series of trest to establish
electrical properties. The results includes voltage holdoff,
current carrying capacity and insulation resistance for 2-sided
bare, coated, and encapsulated boards.
Average breakdown voltage (V) followed the relationship
V = 3.1 S(superscript)0.51,
where separation (S) ranged from 0.25 to 1.5 mm.
(This is for bare boards at ambient conditions.)
Current carrying capacity of conductors was evaluated by
temperature rise between conductors generated with step increases
in current. Variations in temperature rise between conductors with
the same nominal or design width were correlated with meaured
differences in conductor cross-sectional areas. Resistances
calculated from conductor lengths and cross sectional areas were
within 10 percent of the measured values.
The boards tested were fabricated using a panel plate and solder
dip or plate and liquid level process. A few measurements were
made on boards fabricated using a pattern plating process with
thin clad laminate.
Testing was "frequently" extended until functional failure to
obtain a better understanding of the failure mode.
IPC published the Jannings paper, "Electrical Properties of
Printed Wiring Boards," as IPC-TP-117 in September 1976.
The results of the study indicated that conductor spacing
recommendations in MIL-STD-275 were very conservative and could be
reduced.
Copies are available from IPC's order dept., email: [log in to unmask]
Mike Buetow
IPC Technical Staff
2215 Sanders Road
Northbrook, IL 60062
P: 847-509-9700, ext. 335
F: 847-509-9798
[log in to unmask]
-=x=-
From: [log in to unmask]
RE> Current Carrying Capacity
Through the *Designers Council*, last week, Davis Benjamin
<[log in to unmask]>, inquired about a mathematical model for the
current carrying capacity of printed board conductive patterns.
Then Leonard Bendikeen <[log in to unmask]> inquired about the
IPC*s-D-275 thermal rise above ambient -vs- current charts and
commented they came from the MIL-STD-275, and expressed concern
about trying to duplicate the measurements and data. Lastly, Doug
McKean <[log in to unmask]> sent an *off technet* e-mail
to me remembering I had posted a previous comment on
current-carrying capacity and expressed some concerns about the
existing tables/charts, and to re-stimulate what is one of my
concerns and is somewhat a high-interest-button.
In my files, back in April 8-11, 1996 time frame some questions
were raised on technet concerning *fusing current* and *current
carrying capability* of printed board conductive patterns. These
are/should be available from the IPC*s technet archives.
In summary, to the best of my knowledge, (with one exception) I*ve
never seen a mathematical model of the *thermal-rise above ambient
temperature* for the current carrying capacity of printed board
conductive patterns. Leonard was right in his comment in that it
is difficult and labor intensive to perform all of the dimensional
measurements. What adds to the problem is that with low cross-
sectional area (width/thickness) ration conductive patterns the
conductor width tolerance has a more significant effect on
cross-sectional area that thickness. In contrast, high
cross-sectional area *wide* conductive patterns (such as
power/ground conductors and planes), the thickness has more of an
influence on conductor resistance.
The following is a copy of some of the stuff that was presented in
the April 8-11, 1996 response on technet.
Current carrying capacity of conductors for printed boards.
Several decades ago, (to my remembrance) the US's NBS (National
Bureau of Standards) conducted some of the first documents current
carrying capacity and thermal rise above ambient tests for UL. The
results of this testing and subsequent testing has resulted in the
current-carrying capacity -vs- thermal rise above ambient in the
two main design standards, the old MIL-STD-275, and IPC's D-275,
Table 3-4. The original NBS/UL studies used a test procedure and
test specimens much like IPC-TM-650, Method 2.5.4.1. Memory seems
to recall though that the first tests were performed with the test
conductors horizontally, but the test printed board was "hung"
vertically. Then in the second set of testing (and I believe all
subsequent testing to date), the test printed board was suspended
horizontally with the test conductor located on the lower side.
The reason for the change was that with vertical mounting of the
printed board there was preferential convective cooling of the
test specimen that was not a worst- case like condition of an
in-use horizontally mounted printed board. Care must be exercised
in looking at the test data and results because most have used 0.8
mm [0.03 inch] and others have used 1.5 mm [0.06 inch] thick base
materials. CAUTION must also be used when you use the tables
because they do not include any polymeric coatings over the
conductive patterns (such as solder resist).
IMO, the key to understanding the IPC-D-275, Table 3-4
current-carrying capacity -vs- thermal rise, like most of the
other tables, is to realize the table is the result of "avg" test
data, and that many of the "tables" are a redraw of a redraw of a
redraw. I've collected about a dozen variations of a Table 3-4
like table, they're all similar, but each illustrator has taken
some liberty by "cleaning up the drawing" in the redraw. Aside
from this, at home on my own is I've collected all of the raw test
data that I've been able to find from both published articles and
personal correspondence, I've also back-digitize all of the tables
I've got, then all of this has been entered into a spread sheet
data base, now I'm in the process of overlaying the heat transfer
modeling for conductive, convective and radiative heat transfer
functions and develop a best reasonable set of coefficients and
factors for a best curve fit. I'm also attempting to include the
effects of solder resist. The goal is to have something based on
physics and correlation to test data, and not redrawing the
drawings for publishing clarity. And yes, I've been derelict in
my duties to comment on some IPC documents, I've observed most
tables contain a unique physical capability --- (;-) (;-) (the
smilies are to indicate the following is presented in jest, though
serious, and not to tweak too many of you off at me) both Table
3-4a and 4c have a unique electrical capability. Look at the
origin and you will note that with one exception you can have
current flow of up to 250 mA with a conductor of 0 (zero)
cross-sectional area. Now that's one heck of a current source --
I wish I had one that worked that way. (;-) (;-)
In theory, the "power density per unit area and thermal rise above
ambient" should be a constant. Also in theory, if you double the
current and quadruple the cross sectional area (the ol' electrical
power I squared R power law) the power density and thermal rise
should be a constant. However it's not, and IMO is because the
additional heat and area changes the thermal (heat transfer)
characteristics (coefficients). At work, we have found it is a
reasonable approximation for you to extend the slope of the tables
thermal rise above ambient. We've done this for surface
conductors limited to 20 degrees C above ambient and currents up
to 50 Adc, though you need to verify it for your application.
End of the April 8-11 response, the following are some *new*
comments/thoughts.
To the best of my knowledge, all of the existing published charts
are based on quantitative electrical tests performed on test
specimens and the thermal rise is calculated from the conductor*s
electrical resistance at various current flows. The *charts* are
made to look like *graphs* by using a *french curve* to *best fit*
the lines between and beyond the data points to make it look-like
a graph; in many cases, the data points have been removed to make
the chart *look-like* a graph. We can*t knock the rock too hard
though because the charts/graphs have been working very well for
several decades with very few problems.
In a past life, we had many applications where we need to extend
the existing thermal rise charts beyond their published ranges. A
review of existing journals revealed the IPC/MIL-STD were the
basis of most charts. Some industrial companies had developed
their own (proprietary) set of requirements. Several studies have
been reported and there is some variation in reported data between
the various studies, which seems to be due to differences in the
test specimen and the test chamber.
Back in August, I FAX*d to the IPC*s technical staff personnel 9
pages some concerns, examples and suggested solutions I had about
the Table 3-4 in D-275. In addition, I supplied comparisons with
other charts for consideration in the revision of the D-275 to the
2221 design document. The big problem I had with Table 3-4a is
that at the origin you can have electrical current flow with *0"
(zero) cross-sectional area for conductor thermal rises greater
than 20 degrees C * IMO that defies the rules of physics and
mother nature. Close examination of Table 3-4a reveals that on
the 10 degree C curve, there is a *hump* in the curve between
about 30-to-200 sq. mils. conductor cross- sectional area. (IMO,
the one in MIL-STD-275D is better, it converges to the origin and
the *slope* of the charting is more uniform.)
The following highlights some of the concerns, observations I*ve
made, and data I*ve collected. Once again, up-front, I*ll
apologize about the length of this response, it*s not a simple
problem/subject, but it should bring us up to date on the
historical (or hysterical (;-} ) background and concerns about
the graphs. More importantly though, the following is to
stimulate interest in our industry to develop a published set of
mathematical models for *reasonably* predicting the thermal rise
above ambient for printed board conductors.
Back in the infancy of printed boards, (possibly even before the
IPC) current-carrying capacity of printed board conductive
patterns was a design, functional and reliability concern. Designs
were mostly *single-sided* and later *double-sided* printed
boards. Conductors were relatively large, and electrical currents
(for radio/television tube filament currents) were fairly high
(100's of milliamperes). In the mid- to late-*50's, the some of
the first publishing of thermal-rise above ambient -vs- current
carrying capacity was published. The *How to Design and Specify
Printed Circuits* book, published by the IPC in *57 on page 35.
The chart in this book has been re-drawn by *re-scaling* the
ordinate or abscissa axes and used in many subsequent books,
standards and specifications. The first *complete* set of data
and description of the test specimen I*ve located is in the
*original* revision of the EIA*s RS-251, October 1961, *Test to
Determine Temperature Rise as a Function of Current in Printed
Conductors*.
The EIA*s RS-251 Thermal Rise Test -
The test specimen is described as a 1.6 mm (0.0625 inch) thick
XXXP-26 (paper phenolic) 70 micrometer (2 oz./sq.ft.) thick copper
conductive patterns. The conductor widths are 0.635 mm (0.025
inch), 1.27 mm (0.050 inch),1.905 mm (0.075 inch), and 2.54 mm
(0.100 inch). The test printed board test specimen is ~142 mm
(5.6 inches) *high* by ~366 mm (14.4 inches) *wide*. The
following is an attempted sketch of the test specimen:
|-------------------- top edge of the board ---------------------|
25.4 mm (1 inch) edge-to-conductor center line
O------------T------------------------T------------O
30.48 mm (1.2 inch) conductor center-line spacing 3 places
O------------T------------------------T------------O
O------------T------------------------T------------O
O------------T------------------------T------------O
25.4 mm (1 inch) edge-to-conductor center line
|------------------ bottom edge of the board -------------------|
The *O*s* represent the lands for the attachment of the current
source wiring. The *T*s* represent a *T* tap for the attachment of
the voltmeter connections. The distance from the left and right
edges of the board to the *O*s* is 30.48 mm (1.2 inches). The
centerline spacing between the lands (*O*s*) and the *T* taps is
~75 mm (3 inches). The centerline spacing between the *T* taps is
~150 mm (6 inches). The one conductor is tested at a time, a low
current (~100 mA) was used for a *short* time in order to
determine the *ambient* electrical resistance. Three levels of
electrical current were used to determine thermal rise for the
0.635 mm wide conductor, 7 levels of current were used for the
1.27 mm wide conductor, and 6 levels of current were used for the
remaining conductor widths. In the EIA*s Figure 2, the thermal
rise above ambient was calculated and limited to be less than 60
degrees C. The 1.27 mm wide conductor was calculated to be about
72 degrees C and the 1.905 mm wide conductor was calculate to be
about 78 degrees C above ambient.
Comment * as mentioned before, I heard comments this testing was
conducted by the USA*s NBS (now NIST). I also have heard comments
that the thermal rise above ambient data for printed board
conductive patterns was obtained through the wire/cable
organizations * don*t know.
Other Info -----
The exception to mathematical modeling was *Current Carrying
Capacity of Fine-Line Printed Conductors*, by A. J. Rainal, was
published in *The Bell System Technical Journal*, Sept 1981. This
some what mathematically modeling was for specific printed board
configurations and does not seem to be a *universal* model for
general use (though it*s good information).
Charlie Jennings, (now retired from Sandia National Laboratories -
Albuquerque) was an IPC Task Group Chairperson, and conducted a
study on the *Electrical Properties of Printed Wiring Boards*. His
technical paper is available through the IPC as IPC-TP-117, and
was presented at the IPC*s meeting in September 1976. I contacted
Charlie a few months ago and he was graciously able to supply me
with some of the test data that was not published in the report
from his files. In this test program, they used a different test
specimen (not the EIA*s). The conductor lengths were about 25
and 51 mm long and the conductor spacing was 4.4 mm.
As mentioned in the report, the results are somewhat lower that
previously published test data, this is presented in Figure 16 of
TP-117. For the same conductor width (1.27 mm) and current (4
Adc), the thermal rise above ambient for Weick and Nobel is about
12-14 degrees C, for MIL-STD-275 and IEC-326 it*s about 6 degrees
C, and for TP-117 it*s about 4 degrees C for the 51 mm long
conductor and about 3 degrees C for the 25 mm long conductive
pattern. This is shown in a chart as Figure 21 of TP-117.
Comment * I suspect the *thermal loading* of the test conductors
due to the proximity of the lands in the design of the test
specimen..
Charlie references a couple of papers that could be of interest,
R. P. Nobel, *Temperature Rise vs Current Rise of Etched Wiring
Lines*, Elect. Mfg. July 1957. Another one is W. Weick,
*Measuring Printed Circuits Current Carrying Capacity*, Western
Electric Engr., 5, pp 39-41 (1961). A third on of interest might
be M. E Friar and R. H. McClurg, *Printed Circuit Conductor Widths
for High Current Applications*, Int. Electronic Circuit Packaging
Symposium, 9'th Symposium Paper 6/2, 10 pages, August 1962. (I
suspect though these are based on *lab tests* and data plots).
(If any of you know where I could obtain copies of there reports
it would be appreciated, Ralph)
Ralph*s Technical Concerns --
First * they*ve been working for years with little/no problem * so
why rock the boat????
As previously mentioned, the test data is based on a
*single-sided* conductive pattern that is horizontally oriented,
on a test specimen that is *hung* (vertically suspended) in a
*suitable* test chamber to limit circulating room air currents.
Cooling Mechanism * the intended cooling mechanism is *natural*
convective air flow. Most of the conductor*s heat will be
transferred to air by either laminar (or at higher temperatures
turbulent) air flow. (IMO most probably all heat transfer is
laminar near the conductors.) If it were pure *free* natural
convective cooling, then the traditional thermal design equations
for free convective air heat transfer would match the printed
board conductor thermal-rise above ambient charts --- they don*t.
The general convective heat transfer equation is in the form of:
q = k As-f dT^n
Where q is the quantity of heat (electrically Watts), k is a
constant to reflect units of measure and other stuff As-f is the
effective area of the conductor*s surface-to-fluid (air in our
case) dT^n is the differential temperature raised to some power
*n* which is the thermal transfer coefficient from a solid (the
conductor) to a fluid (air). *Generally* for *free air* this *n*
coefficient is about 1.25-1.27.
The various *free air* coefficients are based not on a relatively
small conductor on an large insulator (electrical and thermal),
rather they are based on some form/shape of a large *metal* fin
that has *free air* circulation from the bottom edge around both
sides and converging at the top --- this is not out general
printed board. In addition, the *test specimens* do not have heat
generating components mounted on the assembly. In addition, many
printed boards (and their assemblies) are mounted horizontally and
the heat transfer coefficients between a *bottom mounted* heat
source and a *top mounted* heat source are quite different. In
other words, our *conductor thermal-rise above ambient temperature
for conductor width and current density* isn*t to representative
of the product*s application requirements --- but I*ve been
reminded (several times) *it been working with little/no problem*.
So What*s Ralph Been Doing???---
After analyzing and reviewing *the problem* I decided my first
contribution would be to identify a set of mathematical equations
that would *duplicate* the existing Tables/Figures/Charts. I took
all of the published charts I could locate and *blew them up*
(photographically enlarges them) until the ordinate and abscissa
axis were respectively about 8.5 by 11 inches. The next step was
to *digitize* by interpretative scaling the cross-sectional area
and current axes in a uniform 1,2 and 5 sequence for each axis.
Personal Comment - let me tell you, when you try to scale and
digitize what looks like log scales * are you going to be in for
an eye-opener. Some sections of the chart axis are log, some are
semi-log, some section are almost linear ---- all on the same axis
* what a mess. The next step was to dump the *digitized* data
into a spread sheet for each thermal-rise above ambient to graph
current as a function of cross-sectional area. Up to 5 different
(sources) of digitized (interpolated) data from the charts was
compared to identify the *grossness* of the deviations. Review of
the data suggested the MIL-STD-275 has more consistent. The
spread of the other chart*s data was inconsistent (some were
greater in value and others were less), so the MIL-STD was used as
the base line. Current (non-electrical) status: ----- a series
of *free air* equations, with appropriate coefficients have been
developed that will reproduce the MIL-STD-275 (and the IPC*s-D-275
Table 3-4a) with a *worst- case* of less than a 5% deviation in
current over the existing MIL-STD *charted* values. In a couple
of cases, I*ve biased the deviation in the direction of being
conservative (reduced risk and current) for the particular thermal
rise because adjusting the *k* or *n* coefficients wouldn*t
*curve* match - so I took the conservative (safer way).
So, I*ll try to *clean-up* by re-checking the interpolated data,
re-check the equations that will graph the MIL-STD chart to with
3-5% to technet and provide them to the IPC for consideration for
inclusion in their design standards. I*ll try to get this done no
later than early this Saturday so it*ll be out prior to leaving
for the IPC*s meeting next week.
So I*ll close for now, get back to work to compete my IOU*s.
Ralph Hersey
Ralph Hersey & Associates
Phone/FAX: 510.454.9805
email: [log in to unmask]
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