I have done that in the past on boards where I was concerned with the
stackup. Always worked out very well but it required a fab note to prevent
the board house from removing the pads.
Gary
On Wed, Jun 5, 2013 at 4:53 AM, Matthias Mansfeld <
[log in to unmask]> wrote:
> Hello all,
>
> Just a question: If there is exposed edge copper, which is NOT
> electrical stuff, would it be allowed or tolerable? I used to put
> different non-electrical, sufficiently isolated dummy pads on inner
> layers directly on the board edge, staggered like a stair, which get
> milled apart later and thus allow to check the correct layer order
> and stackup with a simple magnifying glass, but learned that the
> board manufacturers don't like any kind of exposed copper and would
> remove this anyway.
>
> Regards
> Matthias
>
> On 3 Jun 2013 at 12:06, James Jackson wrote:
>
> > Is there an IPC callout for exposed edge copper?
> >
> > I seem to remember it not being allowed, but cannot locate an actual
> > statement in any of the IPC documentation.
> >
> > What I am referring to is when you have a negative copper plane (or
> > copper pour) on an internal layer that extends to the edge of the PCB.
> > When it gets fabricated, there would be a small line of internal
> > copper for each of the planes that extend to the edge of the PCB -
> > which could be shorted together, if a metal object were brought into
> > contact with the exposed copper.
> >
> > Any thoughts?
> >
> > Regards,
> >
> > James Jackson
> > Oztronics
>
> --
> Matthias Mansfeld Elektronik
> * Printed Circuit Board Design and Assembly
> Neithardtstr. 3, D-85540 Haar, GERMANY
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