At 09:20 AM 2/18/99 -0500, Dennis Ward wrote:
>I was hoping some of you experienced PCB designer would
>share a few pearls of wisdom with me.
If not pearls, then at least oysters or oyster shells...
[...]
>When a design is first initiated how do you determine the
>proper amount of space versus layer count??
>Right now we are using a 16.5 X 11.2 board, populated
>both sides. Right now we're hoving at 10 -12 layers per
>board. Is there some formula, methodology, metric, etc,etc
>that actually works??
Here's how I do it, in any case. I assign a certain area to each component.
This is the area which would be taken if an entire PCB consisted of nothing
but many copies of this component, and they were packed efficiently but
with sufficient space to allow for clearance and manufacturing. Obviously
the latter consideration may vary with process. Further, for surface-mount
components, the component area must allow space for vias; for SOICS and
many other parts, these vias may be internal to the assembly area, but for
resistors, for example, where it is desired to keep vias out of the space
between the two pads, additional area may be required. In addition, there
should be sufficient space between the component pads, in the event that
assembly could pack them very closely, for at least a single trace.
Then I consider the usable area of the board; this is the board area
available for components, excluding mounting holes, component keep-outs,
etc. If double-sided assembly is being used this might be double that for a
single-sided board, but a little more space should be added to SOIC
spacings, for example, to allow for non-conflicting vias from ICs on both
sides. (Consider two SOICs on opposite sides of the board; one of them can
have a set of vias inboard; unless the vias are small or the packages
large, additional space is needed for the via fan-out for the other one.
This would be a band on either side of the IC pattern, and the average area
per IC would thus be increased by the area of one of those bands.
I divide the former by the latter, which gives me a density figure.
Obviously, anything beyond 100% is impossible, or almost impossible,
without changing *something.* I say "almost" because the area per component
figure may include space for vias or a little extra space for a trace,
where the actual parts might be connectable without vias or that space.
This would depend on the nature of the circuitry and it would be hazardous
to rely on it, to say the least.
Further, the component shapes frequently will not pack efficiently. But,
still, it is theoretically possible to place and rout a board at 100% or
close to 100% density.
In practice, I have designed single-sided through-hole analog boards in
excess of 95% even with only four layers. Nearly all single-sided
through-hole boards can be realized within six to eight layers as long as
the parts can physically be placed. Single-sided surface mount is no
different if space is allowed for vias. Layers beyond that are added for
noise or impedance control, or similar considerations.
Double-sided design, though, can get really hairy, as I am sure Mr. Ward
knows. Still, once via fan-out is achieved, and with a good placement,
double-sided design should not require more than two additional layers, if
that.
What I have not said is how difficult the design might be. I tend to start
charging extra for double-sided design above 50-60%, and for multilayer
design above 65-75%.
Abd ulraHman Lomax dba Trace Engineering
Printed Circuit Design Services since 1975; Tango, Protel, interfaces with
OrCAD
Sonoma, CA USA
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