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April 2008

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Subject:
From:
"Murphy, John" <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Tue, 8 Apr 2008 08:35:10 -0700
Content-Type:
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text/plain (83 lines)
     Thank you Mr. Vischulius for your input, you make a good point.

     Basically, I interpret layer to layer registration on a finished
bare board as the accuracy of alignment of physical features of each
layer with respect to each other.... to match the master artwork layers
exactly aligned,  being the definitive baseline standard from which to
calculate a deviation.  I thought that to be a common interpretation,
perhaps not.   Which is why I ask the question " Is it a good idea to
specify layer to layer registration for Class II"

    I think soldermask to copper pattern alignment is one answer to your
other point.  What I believe makes my issue is that when multilayers are
stacked it is a mechanical process to align layer to layer which can go
wrong if not controlled for a number of reasons (one of which is
scaling).   Granted the annular ring specification addresses drill to
pad concentricity but it does not address layer to layer.  I guess you
could argue that if two pads on adjacent layers were misaligned and
their common plated thru hole were too pass thru both within spec. ,
then all is good.   



-----Original Message-----
From: Donald Vischulis [mailto:[log in to unmask]] 
Sent: Monday, April 07, 2008 7:04 PM
To: TechNet E-Mail Forum; Murphy, John
Subject: Re: [TN] layer to layer registration?

John,

How do you define layer to layer registration?  While this might appear
to be a trivial question, if minimum annular ring and holding master
artwork line widths within tolerance aren't sufficient to define your
needs, what additional requirements have to be met?

Don Vischulis

-----Original Message-----
>From: "Murphy, John" <[log in to unmask]>
>Sent: Apr 7, 2008 12:13 PM
>To: [log in to unmask]
>Subject: [TN] layer to layer registration?
>
>Greetings, 
>
>                  Is it a good idea to specify layer to layer
>registration for Class II 
>
>multi-layer PCB's?  My searching thus far indicates it is not directly
>contained
>
>in any IPC specification (other than annular ring requirements) but
>relegated to 
>
>the Master Drawing. 
>
>
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