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March 2005

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Subject:
From:
"Scott, Ron" <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Tue, 15 Mar 2005 08:00:34 -0600
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Scott,

The way I approach high pin count is to split the BGA into some number
of hetero devices, meaning all parts actually represent one device. It
is probably ideal to have one device but it becomes very cumbersome to
fit on one page with proper pin spacing. For example, I just built a 240
pin Altera PGA and split into two pieces. This allows you to follow the
spec sheet and make a detailed schematics. My Altera has four distinct
logic blocks so I put two banks into each symbol and was able to put
them side by side on my schematic. Hope this helpful. 


Regards,

Ron Scott C.I.D.
Texas Instruments
Tel:  214.567.4715
Cell: 972.816.7978
[log in to unmask]

 

-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
Scott Riley
Sent: Tuesday, March 15, 2005 07:47
To: [log in to unmask]
Subject: [DC] Schematics for high pin count BGA devices

I'm looking for a little information on the best way to represent BGA
components with a high pin count (EX: 484 I/O) in a schematic. I need to
be able to document a schematic for a board that will have two BGA
devices (484 I/O and 165 I/O). Once the customer reviews/approves the
schematic I would extract a netlist and use it to create rats on the
layout and for programmatic comparison.
 
My assumption is that I will need to create symbols that have all the
pins around the perimeter of a square or rectangle, but was hoping
someone could share their  experience on schematics for similar
components and if there is a better/different approach.  
 

Scott D. Riley
Technical Design Service
607-658-9322 - Office
607-785-1696 - FAX
 <http://www.techdesignservice.com/> www.techdesignservice.com

 

 

 

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