I think she was asking for minimums based on ASSY, not FAB
Unfortunately, I can't help either.
We don't do much wave here anymore, almost all reflow.
Do you tent your vias with mask? Ours aren't totally tented,
but we let the mask encroach onto the via pad up to the hole.
( I call 'em "poncho vias" now). With either of those scenarios
your trace-to-via clearance can be the same as your trace-
to-trace, invisible to manufacturing.
I would think as long as your mask is registered well, the
clearance doesn't matter so much. As long as no copper is
exposed, you won't get shorts.
As for pad-to-pad, we have high-count quad flat packs where
the pads are REALLY close together, and we don't have
problems. So my thinking is, if a part can handle 5mil gaps
pad-to-pad, why can't everywhere else?
I'm only talking reflow, of course...
I know that isn't a scientific answer, and if anyone has good
rules for wave I would like to hear them, too
onward thru the fog,
Jack
On 8/28/07, Andre Demers <[log in to unmask]> wrote:
>
> Hi Kitty,
>
> If I understood your question, then the best source would be your fab
> house.
> They can give all their minimum requirements in order to fabricate your
> board,
> and you decide if you can or can't meet them based on electrical
> requirements,
> board density etc .... Basically designing for fab.
>
> Let me know if I'm off base on this.
>
> Regards,
>
>
> Andre Demers, C.I.D.
> Senior PCB Designer, Coordinator
>
> cmrsummit Technologies
> 329 March Road, Suite 203
> Kanata ON K2K 2E1
> Canada
>
> Telephone: 613.599.3881
> Toll Free: 877.428.1229
> Pager: 613.368.0506
> Fax: 613.599.7889
>
> [log in to unmask] <mailto:[log in to unmask]>
> www.cmrsummit.com <http://www.cmrsummit.com/>
>
>
>
>
>
> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
> Kitty Hines
> Sent: Tuesday, August 28, 2007 2:53 PM
> To: [log in to unmask]
> Subject: [DC] Spacing Requirements
>
> Hi,
> I'm trying to revamp some of the spacing requirements that our
> Manufacturing Dept. has decided upon and need some documented proof that
> the spacing they "require" is unnecessary. I tried to find specific
> requirements in IPC-2221, but wasn't able to find them. What I'd like
> to
> find is spacing requirements for pad-to-pad, pad-to-trace, smd land-to
> smd
> land. I'd like to find requirements for solder wave and reflow
> processes.
> Does anyone know what IPC spec I should be looking at? Or a reliable
> reference I can find? These requirements would only take Manufacturing
> rules into consideration, disregarding any electrical rules.
> Thanks for any help you can be,
> Kitty
>
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