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July 1999

DesignerCouncil@IPC.ORG

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Subject:
From:
Lum Wee Mei <[log in to unmask]>
Reply To:
DesignerCouncil E-Mail Forum.
Date:
Wed, 28 Jul 1999 08:02:08 +0800
Content-Type:
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We faced the same thing over here. Just about 2 years back, we particularly
flood whatever space left behind from routing to ground. As for the clock
signals, they have shielded ground taces around them with ground vias punched
along the ground traces. According to the engineers who suggested this, it will
provide an overall shielding to protect the clock line.

As I start to read up more and probe around the web sites to learn more from
those experts out there, to pour ground fills over the layers is something
unacceptable if you have high speed concerns. What you require is a good board
stackup and how you distribute your signals over the layers, especially those
clock and control signals. What is the use of a ground plane adjacent to your
critical signals if it is filled with vias. This plane will not serve its
function as a good return path for your signals. In addition, what is the
purpose of using the ground shield traces. If it is to reduce coupling between
signals, then the best solution is to space them > 2W apart. (King's Rule,
right?). I remember Lee Ritchey mentioned in PCB Asia 97 that by filling up
those unused area with ground will not resolve the problem, instead it may add
more problems. Nothing beat using a plane.

I just want to share what I have just started learning and hope to learn more
from the rest out there.
Regards.


"Hawes, Adam" wrote:

>         I feel sure this is probably an issue for a lot of PCB
> designers......
>
>         Recently, I have come across an increasing number of engineers who
> wish to have certain tracks on multilayer PCB's shielded by ground traces
> running adjacently. It seems to be a case of jumping on the bandwagon to me
> because we never used to do this until about 12 months ago.
>
>         I was under the impression that ground tracks only served a useful
> purpose on 1or 2 layer boards and that on a multilayer they were essentially
> a waste of space as most of the capacitive coupling would be straight to the
> ground plane.
>
>         I don't like to tell the engineers their jobs obviously so can
> anybody put forward their views so I have a more solid argument!
>
>         Thanks all,
>
> Adam Hawes
> PCB Design Eng.
> GenRad Ltd.
>
> Tel: 0161  491 9290
> Fax: 0161 491 9106

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