Hi Stella,
Ron Nowak here at Lockheed Martin Owego packaging applications! Great question on flip chip substrate design! 
Coplanarity is critical when it comes to flip chip "ORGANIC" packaging. I highlight "critical" and "ORGANIC" because the substrate die site flatness (coplanarity) is key when it comes to assuring that the attached die and substrate are reflowed acceptably and in contact with each other for 1st level assembly.  Organic materials do not behave like traditional LTCC and HTCC expensive ceramic materials during and after reflow temperatures.
In other words did all of the flip chip connections make contact with flux and/or solder paste to get reflowed and attached to my organic (FR4, polyimide, flex, PTFE, etc) substrate?

In the 90's we typically had a die site flatness requirement of 37 microns (0,0015") for a die size of 14 mm with a full array of 225 um flip chip connections for organic substrate packaging.
 (IBM patented the C4 term for flip chip: controlled chip collapse connection by Puttlitz and Totta in the 1960's.)
There are many parameters here:
Die size?
Flip chip ball size?
Bump pitch?
Perimeter bump or full array bump?
Stud bump or flip chip bump metallurgy.?
Flip chip pad metalurgy?
Soldermask or non soldermask defined pad?
Soldermask under the die?   Has a direct impact on die underfill dispense...
Underfill? What material?  Underfill is critical to ensure the reliability of the flip chip connection due to the mis match of CTE between the die and the substrate ( 3 ppm vs 17 pmm on average)

What stud bump process are you using?
Another factor that is key if you have soldermask is how you design your flip chip connections? What solder mask registration capabilities does your vendor have? Most PWB vendors can do +/- 0.002 -0.003"...some better with LDI capabilities. You cannot let the soldermask creep onto the flip chip pads.

 I started designing organic flip chip test vehicles for IBM back in the early 1990's and have witnessed the migration from ceramic to organic in 1st level packaging..
What a revolution....
Call if you have any questions...
Regards and good luck!

Ron Nowak
Electronic Packaging Applications
Lockheed Martin MST
1801 State Route 17C MD 0409
Owego, NY 13827-3998
phone: 607-751-2089
cell: 607-427-0870
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Yap, Stella (SMI)
Sent: Sunday, April 13, 2014 9:55 PM
To: [log in to unmask]
Subject: EXTERNAL: [DC] Flipchip pads coplanarity

Hi all,

I design layouts for flip chip process.  The pad pitch is 200um and stud bump height ~50um.  I would like to know if there is any requirement on the flip chip pads coplanarity. That is, is there any specification for difference in max and min copper pad heights on pcb board within the 4 sides of the chip?  I have not been successful in finding any information regarding this area on the internet.  How tolerant is the stud bump process in flip chip?

Also, do you recommend soldermask under the flipchip?


Regards,
Stella


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