oh, sorry for misunderstanding...
What you are asking about is covered under 3.4 of IPC-6012
particularly
"3.4.1 Hole Size, Hole Pattern Accuracy and Pattern Feature Accuracy"

but it is not specified in the way you might think.
because
if the hole pattern and artwork patterns are misregistered too much,
you will be violating your minimum annular ring requirements
(which are defined by the "class" of your design)
So,
look at minimum annular ring in IPC-6012 Table 3-9

onward thru the fog,
Jack

On Tue, Apr 21, 2015 at 9:18 AM, Cables, Tim <[log in to unmask]> wrote:

>  No, this is more of a registration between NPT holes and copper artwork
> issue.
>
>
>
> *Tim Cables*
>
> PCB Design
>
>
>
> *Aclara*
>
> 440.528.7447
>
>
>
> *From:* Jack Olson [mailto:[log in to unmask]]
> *Sent:* Tuesday, April 21, 2015 10:09 AM
> *To:* (Designers Council Forum); Cables, Tim
> *Subject:* Re: [DC] Tooling hole to Artwork tolerance
>
>
>
> I'm not familiar with the phrase "tooling hole to artwork tolerance",
>
> but if you mean the "clearance from an unplated hole to copper",
>
> it is treated the same as the board edge clearance.
>
>
>
> per IPC-2222
>
> 10.1.1 Edge Spacing Except for edge-printed board contacts, the minimum
> distance between conductive surfaces and the
>
> edge of the finished printed board, or a NPTH, shall not be less than the
> minimum spacing specified in Table 6-1 of IPC-
>
> 2221 plus 0.4 mm
>
>
>
>
>
>
>
> On Tue, Apr 21, 2015 at 8:19 AM, Cables, Tim <[log in to unmask]> wrote:
>
> Can anyone tell me what IPC spec this is listed in?
>
> Tim
>
>
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