Jack: The primary reason for recommending thermal relief in the recent
past has been related to pink ring. Direct connects increase the
tendency toward this problem. With the advent of reduced oxide pink
ring should not be a problem; however, if the reducing step is not
well controlled, or layers are baked too aggressively after the oxide
process the relief may not really be there. Also we have heard that
some or all of the direct metallization processes have increased the
tendency toward pink ring.
Pink ring in itself is generally not considered a serious defect;
however, when coupled with certain acid copper brightners ( and
possibly certain cleaners in that process ) "wedge" voids can result.
If you review the article entitled "The Challenge of Ensuring
Conductive Continuity in High Aspect Ratio, Small Diameter Vias" in
the IPC Review Vol 37 No 7 dated August 1996 you will see a reference
to wedge voids including some photomicrographs.
Having said all that I should say that we see a considerable amount of
direct connect and it is running successfully. To be "safest" we still
recommend that thermal relief be used if possible.
[log in to unmask]
______________________________ Reply Separator _________________________________
Subject: Re: DES: VIAS - Thermal vs. Direct
Author: [log in to unmask] at corp
Date: 9/24/96 6:57 PM
Jack,
One key factor to remember in interpreting these responses is
the board thickness involved. Openings in internal plane around
a pwr/gnd via allow epoxy-epoxy bonding in the z-axis which
helps reduce stress to via hole during thermal excursions, etc.
The thicker the board, and the more isolated the via, then the
more important the thermal relief can be.
Regards,
Karl Sauter
Sun Microsystems, Inc.
[log in to unmask]
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Date: Tue, 24 Sep 1996 09:57:03 -0700
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Subject: DES: VIAS - Thermal vs. Direct
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I was thrilled when the subject of thermal vias vs. direct-connect vias came
up, because we were just discussing whether we should "go direct" last week.
After reading all the responses... well, I'm just a little worried about it.
Rather than quote everybody, here is a summary of what my boss will read if
I show him this discussion:
Two people, K.Barret and [log in to unmask], have used direct connections
extensively, in all environments, all sizes, varied layer count, no
problems. (and one ships about a million boards per year to prove it)
B.Luthor concerned about heat transfer to plane, one reply stated trace from
SMT pad to via was a thermal in itself. (I would tend to agree on that one)
One side discussion about a PINK RING problem, without enough explanation to
learn how pink ring would affect a board or how it is related to direct vias.
Another side discussion about clearance vs. fab allowance, and another about
reduced clearance (anti-pad) sizes. Won't affect our decision.
A warning from Norm about CTE mismatch and the danger of board damage if
direct connections are used.
One reminder from G.Ferrari about the value of formal test procedures and a
warning that what works for one design may not be appropriate for others.
-=x=-
Thanks to all who participated, this thread came along at the PERFECT time.
Our board vendors don't care WHAT we do, so it is up to us. But before I go
show this to others and we make the decision, are there any other issues
that got left out? any elaboration necessary? any final comments?
NOW THAT I THINK ABOUT IT, ALL OF THE REAL-WORLD RESPONSES WERE FAIRLY
POSITIVE, AND ALL OF THE NEGATIVE RESPONSES WERE KIND OF THEORETICAL..!
Am I misinterpreting? Are there any REAL horror stories out there?
Also, if we remove the thermal apertures from our pwr/gnd via padstacks,
should we replace them with a small aperture to "show" something there, or
just leave it empty? Seems like it would be hard to track down connections
looking at "direct-connected" film, any problems there?
thanks in advance, (and Sorry to those who were tired of this subject)
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