Great name!
Jack Olson <[log in to unmask]>
Sent by: DesignerCouncil <[log in to unmask]>
05/31/2007 10:22 AM
Please respond to
"(Designers Council Forum)" <[log in to unmask]>; Please respond to
Jack Olson <[log in to unmask]>
To
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Subject
Re: [DC] Plated thru hole vias covered with soldermask on both sides with
HASL
You are mixing terms a little bit.
Soldermask is an epoxy (the green stuff)
HASL is metal, levelled with hot air
Anyway, we have been using the method
you describe to let the soldermask flow
up onto the via pads, but not into the hole,
So the soldermask clearance is "drill size
plus tolerance". The .15 is a good number
We haven't expereinced ANY fab or assy
problems using tis method.
BTW,
I invented a new name for these last week
when we were at the CID+ training:
"PONCHO VIA"
Jbro
On 5/31/07, Sanchez-Benavides, Erika <[log in to unmask]>
wrote:
>
> Hi!
>
> Due to the wave soldering process for PTH components, our assembly
> process guideline
> indicate to cover vias with soldermask in those areas.
> But as you know, Plated thru hole vias covered with soldermask on both
> sides with HASL
> solder or other manufacturing chemicals might be clogged in the vias and
> out-gas (blow out)
> during assembly or remain in the hole and corroid the copping in the
> via.
>
> There are two suggestions from our PCB suppliers:
>
> Resolution1: PCB supplier to add a clearance to the soldermask: (drill
> size plus.15mm).
> With this option, we are not going to have the via covered, but
> I am not sure if this is enough
> to avoid problems (pearls, solder passing through the via...)
> during wave soldering process.
>
> Resolution2: PCB supplier will tent the vias on both sides by adding a
> barrel relief to prevent their
> assembly problems.
>
> In your opinion, what would be the best option? Is there an alternative
> option you may see?
>
> Thank you very much in advance,
>
> Erika E. Sanchez
> Siemens VDO
> Guadalajara Development Center
> E-Mail: [log in to unmask]
> Internet: http://www.siemensvdo.com
>
>
>
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