Clare,

I would check with the manufacturer of the part, or one of their sales
reps/FAE's.  They may be able to provide you with an example breakout for
your particular BGA that they have tried and works.  The question will be
whether or not it meet your overall requirements.

Good luck,
Devon - C.I.D.



-----Original Message-----
From: Hillman, Clare [mailto:[log in to unmask]]
Sent: 20 October, 2005 9:41 AM
To: [log in to unmask]
Subject: [DC] DDR2 Routing


Hello All

I don't know if this is the correct forum to post this question so
apologies if it isn't.

I'm currently in the process of placing and routing the AMD Au1200 on a
PCB layout.

I'm having a number of issues with the routing of the DDR2 nets from the
Processor BGA (372 pin FBGA) to the 4 DDR SDRAM (84 pin FBGA) devices.
The problem I have is how to route the nets from the Au1200 to the SDRAM
BGAs whilst maintaining the DDR2 routing requirements i.e. minimum
signal spacings of 0.012" within data groups, match net lengths, minimum
number of vias, all nets within each group to be routed on same layers
etc.  The main areas I'm having difficulties is routing through the
SDRAM BGA pins and vias.

The current status of the layout is that it is 8 layers and uses only
plated through vias.  We are reluctant to use blind and buried vias.

If anyone has experience in DDR2 routing, I would be very grateful for
any help or guidance on how to implement these requirements.

Kind Regards
Clare Hillman C.I.D.

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