Couple comments from an old retired guy:
Pull back on internal layers can be determined by the environment the
board will be used in as well as manufacturing issues. As someone noted,
moisture can get into the glass laminate (which is why PCB manufacturers
bake the laminate before using it to make a board). I have seen a PCB
come back from the field with internal layers corroded until board
failure because the device was in a far more humid environment than we
expected. So for those items we started using 50-100 mill pull back. The
outer layers are protected by plating and mask, and they have air
circulation. Once water gets into the internal layers it stays there and
goes "oh look - bare copper - yum".
I have worked on a couple of boards where the planes were taken to the
board edge. RF signals were routed internally with a reference plane.
The outer layers were solid ground. And the boards were edge plated,
making the board an enclosed shielding box with just coax connectors
outside. Don't know if anyone does that anymore.
On 1/7/2016 9:25 AM, Jack Olson wrote:
> I'm not sure which posts you are referring to.
> The only one I saw related to "external" is a modification of the rule for
> card guides.
>
> maybe it is the term "conductive surface"?
> I don't think that term means "external",
> (maybe it should be changed to "conductive feature"?)
>
> Anyway, the standard does not differentiate between internal and external
> layers.
>
> Jack
>
> On Thu, Jan 7, 2016 at 10:51 AM, James Jackson <[log in to unmask]> wrote:
>
>> I have not opened my mouth yet on this discussion because I got a little
>> confused early on.
>>
>> The original poster's question was about 'Internal' Planes and clearances
>> to the board edge. (unless I got that wrong.)
>>
>> I have seen a LOT of discussion about external layers and board edge
>> clearances.
>>
>> I feel like Charlie Brown in the cartoon when everyone is looking at the
>> clouds and telling what they see, and they are seeing all sorts of abstract
>> images. It gets to Charlie Brown who responds with something like, "I was
>> going to say a horsee..."
>>
>> Regards,
>>
>> James Jackson
>> Oztronics
>>
>>
>>
>>
>> On 2016-01-07 10:42, Jack Olson wrote:
>>
>>> Bill, I assumed that you would already have the actual text of the
>>> IPC-2222
>>> standard, but I should have included it for everyone:
>>>
>>> 10.1.1 Edge Spacing Except for edge-printed board contacts, the minimum
>>> distance between conductive surfaces and the edge of the finished printed
>>> board, or a NPTH, shall not be less than the minimum spacing specified in
>>> Table 6-1 of IPC-2221 plus 0.4 mm. Printed boards that slide into guides
>>> shall have a minimum external conductor to guide distance of 1.25 mm or
>>> minimum electrical clearance (see Table 6-1 of IPC-2221), whichever is
>>> greater. Special design applications in areas such as high voltage,
>>> surface
>>> mount, and radio frequency (RF) technology may require variances to these
>>> requirements.
>>> Ground and heat sink planes may extend to the edge when required by
>>> design.
>>> Design should provide sufficient edge spacing to avoid unnecessary haloing
>>> and crazing rejections. Rejections can occur when the edge defect is
>>> greater than 50% of the clearance to edge spacing. Brittle material or
>>> heavier glass weights increase this risk.
>>>
>>> and Table 6-1 mentioned above is the minimum clearances based on voltage
>>> levels
>>>
>>> What bothers me a little bit about the text above is that the first
>>> sentence contain a SHALL (or more specifically, a SHALL NOT), and then a
>>> following sentence says "Ground and heat sink planes MAY extend to the
>>> board edge when required".
>>>
>>> The proposed text for the next IPC-6012 acceptability document says:
>>>
>>> When edge spacing is not designed in accordance with IPC-2222, evaluations
>>> for nicks, crazing and haloing shall be AABUS.
>>>
>>> I'm predicting some extra AABUS discussions (between User and Supplier)
>>> when designers start sending data that has copper planes extending all the
>>> way to the board edge, because some well-meaning engineer or supervisor
>>> claims it is "required". And when the designer gets questioned why he
>>> would
>>> do such a thing (board routing tolerance will certainly leave exposed
>>> copper on one board edge or the other, and possibly smear the planes
>>> together, unless the fabricator modifies the data to get a reasonable
>>> minimum clearance) he will simply state that the design IS in accordance
>>> to
>>> IPC-2222, because it says the designer MAY do this if someone claims it is
>>> required. But that's probably not the question you were asking...?
>>>
>>> Jack
>>>
>>> On Wed, Jan 6, 2016 at 4:01 PM, Jack Olson <[log in to unmask]> wrote:
>>>
>>> Hi Bill,
>>>> *Personally: *
>>>> I always use at least 20, prefer 30, and if it's a large board with
>>>> plenty
>>>> of space, I go 50.
>>>>
>>>> *Fabrication:*
>>>> I've heard if you get near 11, they get nervous and you might get a phone
>>>> call (overheard in IPC discussions). I've also heard that some designers
>>>> want to go all the way to the edge, so they let the fabricator "trim
>>>> back"
>>>> the minimum amount they need to settle their nerves, but in my opinion,
>>>> this is a cheesy design practice and I wouldn't recommend it.
>>>>
>>>> *The Problem:*
>>>>
>>>> If designers reduce the distance from the board edge to the nearest
>>>> conductive features, it creates a hazard for the fabricator, because
>>>> several of the acceptance criteria are based on a percentage of that
>>>> distance. For example, if the router makes "nicks" in the edge, they are
>>>> acceptable as long as they don't extend 50% of the distance to conductive
>>>> features. The more you reduce that distance, the more risk of creating a
>>>> rejectable product, or at least an inspection/approval headache. So, the
>>>> committee is proposing a change to the wording of the IPC-6012
>>>> acceptability document to be:
>>>>
>>>> 3.3.1 Edges When edge spacing is designed in accordance with IPC-2222,
>>>> nicks or crazing along the edge of the printed board, edge of cutouts and
>>>> edges of non-plated holes are acceptable provided the penetration does
>>>> not
>>>> exceed 50% of the distance from the edge to the nearest conductor or 2.5
>>>> mm [0.0984 in], whichever is less.
>>>> When edge spacing is designed in accordance with IPC-2222, the distance
>>>> between the haloing penetration and the nearest conductive feature shall
>>>> not be less than the minimum lateral conductor spacing, or 100 μm [3,937
>>>> μin] if not
>>>> specified.
>>>> When edge spacing is not designed in accordance with IPC-2222,
>>>> evaluations
>>>> for nicks, crazing and haloing shall be AABUS.
>>>>
>>>>
>>>> onward thru the fog,
>>>> Jack
>>>>
>>>> On Wed, Jan 6, 2016 at 3:00 PM, Brooks, William <
>>>> [log in to unmask]> wrote:
>>>>
>>>> Why "surprising" Frank? I like to generate discussion... I like to see
>>>>> what others are doing... I'm not lost or looking for guidance, per se.
>>>>> I'm
>>>>> soliciting opinions, reasons and practical usage by other designers like
>>>>> me...
>>>>>
>>>>> From a strictly manufacturing point of view you should always have some
>>>>> pull back on internal copper plane layers.
>>>>> Meaning... the internal copper planes should not extend all the way to
>>>>> the routed edges of the board.
>>>>> Why? Because the board material needs it to bond at the edges during
>>>>> lamination and also to provide a seal at the edges from moisture
>>>>> incursion...
>>>>> and you really don't want a copper burr along the edge of the board that
>>>>> could short to anything that touches the edge if the copper plane gets
>>>>> exposed.
>>>>>
>>>>> The question is how much pull back do you think is enough for a typical
>>>>> multilayer FR4 board?
>>>>> Some cad tools have a default setting... Altium defaults to 20 mils.
>>>>> What's your common practice? What do the glass/epoxy board manufacturers
>>>>> prefer?
>>>>>
>>>>>
>>>>> William Brooks, CID+
>>>>> Printed Circuit Designer
>>>>> 2747 Loker Ave West
>>>>> Carlsbad, CA 92010-6603
>>>>> 760-930-7212
>>>>> Fax: 760.918.8332
>>>>> Mobile: 760.216.0170
>>>>> E-mail: [log in to unmask]
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> -----Original Message-----
>>>>> From: Frank Kimmey [mailto:[log in to unmask]]
>>>>> Sent: Wednesday, January 06, 2016 12:37 PM
>>>>> To: (Designers Council Forum); Brooks, William
>>>>> Subject: Re: [DC] pull back clearance on internal planes
>>>>>
>>>>> William,
>>>>> This is a bit surprising from you but, it all depends on what you are
>>>>> targeting.
>>>>> If you want to make life easier for you fabricating then you will need a
>>>>> minimum of whatever your positional tolerance for routing are.
>>>>> If you are looking to minimizing your risk for leakage (i.e. High Speed,
>>>>> RF, etc.) you will need to add to the clearances. I stopped pulling back
>>>>> planes and just accepted the minor cost hit (quicker on the design time
>>>>> and
>>>>> not enough signal issues to warrant the added time to create keep outs).
>>>>> In the more sensitive stuff, I like to keep 50 mils back and add ground
>>>>> guards when there is enough room.
>>>>> So I guess this another of the it depends kinda answers, what are the
>>>>> criteria you need to meet and what trade-offs are acceptable.
>>>>> I don't think there are real minimum requirements, but there may be good
>>>>> practices to follow for you specific needs.
>>>>> Good luck,
>>>>> FNK
>>>>>
>>>>> Frank Kimmey CID+
>>>>>
>>>>>
>>>>> Sent from my iPad
>>>>>
>>>>> On Jan 6, 2016, at 12:02 PM, Brooks, William <
>>>>> [log in to unmask]> wrote:
>>>>>
>>>>>> What do you recommend for clearance from the edge of an internal plane
>>>>>>
>>>>> to the board edge?
>>>>>
>>>>>>
>>>>>>
>>>>>> William Brooks, CID+
>>>>>> Printed Circuit Designer
>>>>>> 2747 Loker Ave West
>>>>>> Carlsbad, CA 92010-6603
>>>>>> 760-930-7212
>>>>>> Fax: 760.918.8332
>>>>>> Mobile: 760.216.0170
>>>>>> E-mail: [log in to unmask]
>>>>>>
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