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| Reply To: | (Designers Council Forum) |
| Date: | Thu, 6 Oct 2011 14:24:56 +0000 |
| Content-Type: | text/plain |
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Heather,
All of the major IC manufacturers have Application notes available with design guidelines for their QFN packages. I've found these Ap notes to be extremely helpful as they provide recommendations not only for the pcb footprint but also for stencil design.
We've successfully placed many QFN packages of all sizes using these notes.
Good luck
Arlene Fox, CID
Enercon Technologies
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Heather Gregg
Sent: Wednesday, October 05, 2011 9:39 PM
To: [log in to unmask]
Subject: [DC] QFN layout
Dear Designer Council,
I have recently joined a company which is having great difficulty with
soldering on a QFN part. The main trouble is solder voids under the
component leads, resulting in opens or intermittent operation. One thing I
noticed is that this particular layout has a silkscreen outline under the
part, between the lead lands and the thermal land. I would think silkscreen
under a QFN would be a bad idea. What is the prevailing wisdom regarding
this in the layout world?
Thank you,
Heather Gregg
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