DFX also means Design For eXcellence :-)
Just so happens that I am doing some review of this topic right now, gathering data for a company guideline.
Already have input from Jabil and NBS. Also an unfinished 2003 pdf from Tom Hausherr of PCB Libraries.
If you don't mind sharing, feel free to send me your reference docs or URLs for my studies.
Thanks,
Bob McCreight, C.I.D.
IPC Designers Council
Silicon Valley Chapter
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--------------------------------------------
On Tue, 9/16/14, Brooks, William <[log in to unmask]> wrote:
Subject: [DC] DFM, DFA, DFT, DFX
To: [log in to unmask]
Date: Tuesday, September 16, 2014, 3:31 PM
I recall discussing DFM
awhile back and it occurs to me that there is one additional
area that belongs in the DF'X' family of Design
Practice Criteria...
Design
for Reliability... :)
William
Brooks, CID+
Senior MTS (Contract)
2747 Loker Ave West
Carlsbad,
CA 92010-6603
760-930-7212
Fax: 760.918.8332
Mobile: 760.216.0170
E-mail: [log in to unmask]
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]]
On Behalf Of Brooks, William
Sent: Monday,
September 15, 2014 10:00 AM
To: [log in to unmask]
Subject: Re: [DC] Vias
The webinar was from 2011 and covered both HDI
solid plated holes in 100um and 200um thick materials for
blind thru hole applications by Mark Lefebvre and High
Aspect ratio thru hole plating using Periodic Pulse Reverse
Plating By Dennis Yee. (I just watched it)
Screaming Circuits has a photo
illustration of an example of what I was thinking
about... http://screamingcircuits.typepad.com/.a/6a00d8341c008a53ef013484716f88970c-pi
I'm told that both Via
systems and TTM can do solid copper filled vias and stacked
microvias... Though I have not had any made for boards I
have been working on yet. Don Carron did a great
presentation for the Designers Council here in San Diego all
about different types of vias and their applications and the
processes to create them... and we talked a bit about this
subject of solid copper vias... One of the concerns was that
the solid copper CTE is very different from the surrounding
epoxy glass and at some point the solid copper would really
create stress in the board around the hole over thermal
excursions from let's say -20C to +80C normal component
operation temperature extremes... or especially during
reflow soldering. So there are probably practical limits on
your board thickness to get away with using this
technology... What the limits are I am not sure...
William
Brooks, CID+
Senior MTS (Contract)
2747 Loker Ave West
Carlsbad,
CA 92010-6603
760-930-7212
Fax: 760.918.8332
Mobile: 760.216.0170
E-mail: [log in to unmask]
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]]
On Behalf Of Brooks, William
Sent: Monday,
September 15, 2014 8:02 AM
To: [log in to unmask]
Subject: Re: [DC] Vias
Copper plated filling of traditional thru holes
vias is real... it is being done.
Please
check Dow's website... nice webinar explains the process
and chemical requirements.
http://storage.dow.com.edgesuite.net/flash_video/electronic_materials/4_27_11%20Webinar/files/default.html?contenttype=A&titlecolor=000000&eventid=291345&key=B619E6875E5601E4BC8415DD4C884730&text_language_id=en&sessionid=1&playerwidth=900&playerheight=675&helpcenter=false&format=wmaudio&mobile=false&flashsupportedmobiledevice=false&helpcenter=false
William Brooks, CID+
Senior MTS
(Contract)
2747 Loker Ave West
Carlsbad, CA 92010-6603
760-930-7212
Fax:
760.918.8332
Mobile: 760.216.0170
E-mail: [log in to unmask]
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]]
On Behalf Of iTech iCollege iSrael ????? ?????????? ?????
Sent: Sunday, September 14, 2014 6:56 AM
To: [log in to unmask]
Subject: Re: [DC] Vias
Filled Vias can be made only for microVias, not
traditional Vias which can be tented or covered
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]]
On Behalf Of Varughese, Renjith
Sent:
Friday, September 12, 2014 4:58 AM
To: [log in to unmask]
Subject: Re: [DC] Vias
Hello Veronica,
Solid Copper filled vias you mentioned are
about micro vias or traditional through hole vias?
Thanks and regards,
Renjith Varughese
Honeywell Honeywell Technology
Solutions Lab Pvt. Ltd Adarsh Prime Project Pvt Ltd Survey
No 19/2, Devarabisanahalli Village, K.R. Puram Hobli
Bangalore East Taluk Bangalore - 560 103 Phone # - 26588360
Extn 50211
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]]
On Behalf Of Anderson, Veronika
Sent:
Friday, September 12, 2014 4:28 AM
To: [log in to unmask]
Subject: Re: [DC] Vias
Bill,
Can you
clarify your definition of "copper filled via"?
As far as I know, there is no via filling
material that can be called a "copper fill".
As you mentioned, the thicker plating improves
the thermal transfer and current carrying characteristics of
via.
I've seen the drawings with a note
"vias can be plated shut".
However, the conventional plating process
cannot close the via completely - there is always an air gap
in the middle.
The Reverse Pulse Plating
Process provides the "solid copper plated via". So
far only a few PWB manufacturers do that.
If
you use a solid copper plated vias in your designs, please
share a name of PCB manufacturer that builds your boards.
Regards,
Veronika Anderson C.I.D | Sr.
Electrical/Mechanical Design Engineer | Excelitas
Technologies
Office: +1
626.967.9521 x 236
1330 East Cypress Street,
Covina, CA 91724 USA [log in to unmask]
www.excelitas.com
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]]
On Behalf Of Brooks, William
Sent: Thursday,
September 11, 2014 9:31 AM
To: [log in to unmask]
Subject: Re: [DC] Vias
Peter was talking with me about using vias in
thermal pads and how some still leave an open aperture the
size of the thermal pad for their solder paste...
This can cause the solder paste when it melts
to be wicked down the via holes starving the part for
solder... depending on the diameter of the vias and how many
there are...
One method to reduce this
effect is to change the stencil aperture to a pattern that
avoids the vias and helps distribute the paste over the
thermal pad area evenly...
See this
illustration by Texas Instruments...
http://www.ti.com/ods/images/SNLS302D/sample_layout_DAP_snls302.png
Another thing that helps is to
reduce the diameter of the via to reduce its wicking
volume... smaller holes wick less...
I have
used .008 in. diameter vias for that purpose before...
Or... you can have the via
holes filled and planarized... thus no extra solder is
wicked down the holes...
Partial filling
tends to cause problems...
For example:
Trapped gases will expand in the high heat of the reflow
oven and cause solder balls to occur...
This
is bad for your design when installed in the electronics
application it typically must work in because solder balls
are conductive and can cause shorts between pins and exposed
pads or get loose in vibration and bounce around to other
assemblies and cause the same sort of problems.
Also I have found that filling
vias with solder does not improve their thermal transfer
characteristics very much... Solder is not that great a heat
conductor. Copper is the best thermal conductor typically
for our PCB applications... so thicker copper plating in the
holes or copper filled vias are bound to be far superior for
thermal transfer reasons than filling the vias with
solder.
William Brooks, CID+
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