Sections 7.2 and 7.3 of "High-Speed Digital Design" by Howard Johnson provide
rough approximations for these, along with explanations of their limits.
Recommended reading.

C (in pF) = (1.41*Er*T*D1)/(D2 - D1) where
D2 = diameter of clearance hole in ground plane(s) (in.)
D1 = diameter of pad surrounding via
T = thickness
Er = dielectric constant

L (in nH) = 5.08*h*(ln(4*h/d)+1) where
h = length of via (in.)
d = diameter of via

Assuming 10 mils ground plane clearance, and FR4 Er of 4.5, these give

13 mil via, 0.51 pF, 1.05 nH
17 mil via - 0.69 pF, 0.95 nH


Greg Bordash wrote:
>
> To the DC world,
>
> Does anyone have or know how to calculate the parasitic capacitance &
> inductance on vias ? Is there a formula or chart out there somewhere that
> can be used to determine this.
>
> There are two sizes of vias that I am trying to find values for and they are
> as follows;
>
> 1- Pad 0.026" diameter with a finished drilled hole of 0.013" in 0.062" FR4
> material. (4 & 6 layer designs)
> 2- Pad 0.035" diameter with a finished drilled hole of 0.017" in 0.062" FR4
> material. (4 & 6 layer designs)
>
> Regards, Greg.
>
> Gregory E. Bordash,
> Team Leader, PCB CAD Group
> ATI Technologies Inc.,
> 33 Commerce Valley Drive East,
> Thornhill, Ontario, Canada, L3T 7N6
> Phone:(905) 882-2600 ext: 8370,   Fax: (905) 882-9339
> Email: [log in to unmask]

regards,
Tom Burgess
--
Digital Engineer
National Research Council of Canada
Herzberg Institute of Astrophysics
Dominion Radio Astrophysical Observatory
P.O. Box 248, Penticton, B.C.
Canada V2A 6K3

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