We use Cadence Allegro, and have very good luck with testpoint
placement. Our standard is to run a first pass with 100mil spacing
between the testpoints, a second at 68mil, and the minimum at 50mil. We
use a 30mil pad for the bottom side testpoints, and 35mil for the top if
we have to use a clamshell. We used to put TPs in the schematic, but it
was causing more problems than it solved. We have multiple versions of
via symbols, (solder encroached for the standard via, 30mil pad cleared
on the bottom for the TP version) so we can specify the correct one in
the Allegro tetpoint parameters.
We strive for 100% testability, but it is getting harder to achieve that
on the dense planars and motherboards.
Carol
Carol Keate Chapman, CID+
PG ECAD Design, Sr. Analyst
MS RR5-38
Dell, Inc
501 Dell Way
Round Rock, TX 78682
512-728-4494
-----Original Message-----
From: "Brooks,Bill" <[log in to unmask]>
Subject: [DC] ICT, bed-of-nails and CAD tool support?
Date: Tue, 5 Jun 2007 17:15:38 -0700
'In-Circuit Test' is a seldom discussed subject at the 'designer's round
table' here...
I'm curious how other designers are affected by test points and how they
deal with testability in their designs.
I have placed test points in schematics and treated them as 'components'
on the board before...
What have you seen for test point support from the CAD vendors and is
there an easy way to automate this?
Also those who have to test for a living... what is the process you use
and are the outputs from these CAD tools any help?
Best regards,
Bill Brooks, CID+
------------------------------------------------------------------------
---------
DesignerCouncil Mail List provided as a free service by IPC using
LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with
following text in the BODY (NOT the subject field): SIGNOFF
DesignerCouncil.
To temporarily stop/(restart) delivery of DesignerCouncil send: SET
DesignerCouncil NOMAIL/(MAIL) Search previous postings at: www.ipc.org >
On-Line Resources & Databases > E-mail Archives Please visit IPC web
site http://www.ipc.org/contentpage.asp?Pageid=4.3.16
for additional information, or contact Keach Sasamori at [log in to unmask]
or 847-615-7100 ext.2815
------------------------------------------------------------------------
---------
------------------------------------------------------------------------
---------
DesignerCouncil Mail List provided as a free service by IPC using
LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with
following text in the BODY (NOT the subject field): SIGNOFF
DesignerCouncil.
To temporarily stop/(restart) delivery of DesignerCouncil send: SET
DesignerCouncil NOMAIL/(MAIL) Search previous postings at: www.ipc.org >
On-Line Resources & Databases > E-mail Archives Please visit IPC web
site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100
ext.2815
------------------------------------------------------------------------
---------
---------------------------------------------------------------------------------
DesignerCouncil Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF DesignerCouncil.
To temporarily stop/(restart) delivery of DesignerCouncil send: SET DesignerCouncil NOMAIL/(MAIL)
Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
---------------------------------------------------------------------------------
|
