Hey Michael,

I work for a high volume manufacturer (300 active products with >250K
assy per year)
Here is how we do it:

1. Day one. Testability is critical and should be a part of your initial
design review.
2. We do not assign properties to pins due to the need to test nets not
pins.
3. Functional test points are defined by the Engineer, ICT belong on all
nets.
4. We fan out per the design not per the component geometry
5. Every board should be routed with test in mind (you never know when
volumes or need for test may increase)
6. Fan-out under component should only be allowed if testability can be
achieved elsewhere (fan-out under component is not preferred but is
sometimes required due to density)

Hope this helps
FNK

Frank N Kimmey C.I.D.
EM Designer
C & K Systems, Inc.
916-353-5366
[log in to unmask]
> ----------
> From:         Kuczynski Michael[SMTP:[log in to unmask]]
> Reply To:     DesignerCouncil E-Mail Forum.;Kuczynski Michael
> Sent:         Monday, January 25, 1999 4:18 AM
> To:   [log in to unmask]
> Subject:      [DC] Testabaility
>
> A few questions about testabaility (ICT and functional);
>
> How far along in your design process does testabaility issues start?
>
> Is anyone out there assigning properties to pins that are required for
> testabaility (in symbol generation)?
> If yes, How do the designers recoginize them?
>
> Who defines critical pins? engineer, librarian, component eng.,
> designer
>
> Does anyone build seperate fan-out geoms for the same geom because of
> testability? (per unique p/n, so you end up w/ 4 versions plcc20)
> If yes, do you route on a standard grid or gridless?
>
> Is each board routed with testabaility in mind, even if it is a minor
> volume
> and may never reach a test bed?
>
> Does anyone NOT ALLOW fan-outs under the component?
>
>
> Thanks for your input,
>
> Michael Kuczynski       Librarian/Sr. Designer
> Allied Signal           201-393-2122 (Phone)
> 699 Rt46E E/K4          201-393-2357 (Fax)
> Teterboro NJ 07608
> [log in to unmask]
> [log in to unmask]
>
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