Jack,
I'm not arguing this issue, just trying to understand.
From what I've read general vias are in the same category
as through hole in general...Plate thru-holes.
The blind and buried vias are the only ones that have a description as to
the thickness of the material.
There are several problem/questions I find here. First there isn't a
delineation between soldered pads and unsoldered pads. This is most of the
reasons for land diameter. The difference is whether the pad will be
soldered or not, is it not? Vias are normal not soldered (same as blind and
buried vias) I also don't understand why there is a specification, at all
for b&b vias per thickness. I would believe that this is between you and
your manufacturer. As a guideline I could understand.
Also the issue of annular ring at all, for vias really should be controlled
by the technology, current capacity and guidelines for annular ring over the
hole diameter.
Currently if we had no MFG tolerance to add to the AR then the finished pad
could be less than the hole plating (.005 plating)? That doesn't seem quite
right. Shouldn't both the external and internal pads be defined from the
drilled hole?
I believe this is why most of us say, "this is what IPC says, but this is
what we do".
These are my findings:
Formula for External (soldered) pad
Drilled hole x 15% + MFG tolerance
Formula for Internal pad/via
Drilled hole x 10% + MFG tolerance
Formula for External (unsoldered) pad (via)
Drilled hole x 10% + MFG tolerance
The percent accommodates a larger lead that requires more heat thus
requiring a larger pad.
As for MFG drill-to-thickness tolerance, I believe its around 10%
(example .125 * 10% = .0125" drilled /.008 finished)
I get .125" board with .008"(finished) holes...
Personally I use much larger pads, but this would be a good minimum.
I attached a spreadsheet calculator for your review.
Chris Robertson
[log in to unmask]
<mailto:[log in to unmask]>
Senior Designer
Lockheed-Martin Services Inc.
4912 Research Dr.
Huntsville, AL 35805
(256) 722-2626
Yes, it was a rather silly question to ask -
"Can anyone think of a way to design PCBs to meet IPC with a smaller via?"
because if you say you design to IPC, you have to use the numbers, right?
It is interesting that most all of the answers I got (thanks everyone!)
said something like "yes, the IPC says xxx but we do this..."
and in most cases it seems that although people know what it says,
they go on and do it their own way anyway.
I purposely picked our worst case (over12",>8lyr) to see if anyone had
creative comments, but for anyone reading along looking for answers...
I would probably compromise by designing a via for:
settling for Class 1, which drops the minimum drill size to 15.74 mils
assume less than 12" length typical, which drops the fab tolerance to 9.84
This changes the whole equation to give a via hole 16 with pad 28
I think I could actually design a board with a 16/28 via, eh?
(and for those of you who recommended a 2mil annular ring or an 18/30 via
I'm not arguing your point, that works for me too)
Anyway, thanks again for all the responses, both public and private!
onward through the fog,
Jack, the new guy
-----Original Message-----
From: Ledwinka, Mike [mailto:[log in to unmask]]
Sent: Wednesday, April 25, 2001 7:11 AM
To: The PCD List
Subject: [pcdlist] RE: Minimum Via Size for .093 Thick PCB
Jack,
I see your logic entirely ( rather IPC's) in their quest to be the authority
on PCB standards and the like. These days I haven't used 20 mil via for
routing unless the tracks where carrying high current. And with regard to
that "monster" flash on the drill, I can only chuckle at the difficulties I
would encounter. I tend to use IPC as a ballpark figure or as a basis for
the direction in which I should head when encountering unfamiliar territory.
Seeing the last board I did was 22 layers ( 93 mil thick ), with a 12 mil
drill for bga's and a 13 mil drill for vias. The only reason I used a flash
of 35 mils on the vias was to accommodate probe testing. Its just my
opinion.
Mike Ledwinka
Any replies to this message by previous employers/co-workers is deemed an
attack on my character :)
-----Original Message-----
From: Olson, Jack
Sent: Tuesday, April 24, 2001 4:44 PM
To: DesignerCouncil (E-mail); PCDLIST (E-mail)
Subject: Minimum Via Size for .093 Thick PCB
As a result of some discussion with our in-house manufacturing,
we decided to re-evaluate our minimum via size for .093 board thickness.
Just for fun (grin) I decided to look everything up in the latest IPC specs.
If anyone enjoys poking holes in IPC logic, here is the result:
(see below for supporting references)
calculated IPC minimum via size = 19.7 mil drill with 41.4 mil land
Can anyone think of a way to design PCBs to meet IPC with a smaller via?
-=-=-
Our initial parameters are:
Design for Class 2 (no one is going to die if the product fails)
Assume Level C producibility but prefer Level B (ha!)
Many designs are >12" long
Many designs are >8 layers
According to IPC-2222 Table 9-6,
a plated through via on a board >2mm thick for Class 2 is .5mm minimum
Result: the minimum drill size is 19.68mils
According to IPC-2221 Table 9-1,
For a Level C board up to 450mm dimension (<18inches)
and with note 2 to add .05mm to .45mm for >8 layers is .5mm minimum
Result: Minimum Fabrication Tolerance is 19.68mils
According to IPC-2222 Paragraph 9.1.1
minimum land = a + 2b + c
where
a = maximum drill diameter (19.68mils)
b = minimum annular ring (1mil)
c = fabrication allowance (19.68mils)
Result: minimum land diameter is 41.37mils
A 20 mil hole with a 42 mil pad is difficult to design with.
To meet IPC even at Level C, the only thing I can see to reduce is
the minimum annular ring to allow breakout, are ya kiddin me?
Am I missing something?
Any comments are greatly appreciated!
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