We have some cells (footprints, jedecs, whatever) built that
have two vias built into the end of the smd pads on each end of
the 0402, 0805, and the 1206 for high speed design.  We call them
Dog Bones because that's what they end up looking like. We elongated
the pad slightly so that you have the same solder surface for the
part and the copper of the via and the pad meet.  We have solder
mask cover the via holes and not the surface mount pad.  The hole
size for the via is .013 and we are using VeriBest.

*************************
NVision, Inc.
Tanya Foster
PCB Design
(530)265-1088
(530)265-1055 fax
[log in to unmask]
*************************
Just view the problem as another one of life's
curve balls and practice your batting skills.


-----Original Message-----
From: Barb Zaepfel [mailto:[log in to unmask]]
Sent: Friday, June 11, 1999 8:34 AM
To: [log in to unmask]
Subject: Via holes within SMD pads


I have a situation where the engineer has placed via holes  within SMD
pads, on a double sided PCBoard.
IPC-SM-782 (3.6.3.1 & 2)  discusses geometries used to channel or "neck
down" land areas going to a via to prevent solder migration.
 I am familiar with blind/ buried via technology (IPC-275 5.4.8.4) used for
multilayer printed circuits.  Can anyone give me information on
placing vias within smd pads and does it fall within a Class -2
specification?  Please send any info on Assembly processes used
to  prevent solder migration /insufficient solder fillets, and size
recommendations of the via/technology used. (IPC does not seem to
clearly state that vias cannot be placed within smd pads).
Thanks!

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