Rick,
Actually I have heard of it causing problems, but really only on traces
directly below it on the same layer. Rarely, have I seen traces underneath
them though. There are several ways to prevent traces below. Most have
to do with the program you are using.
1 Is a keepout (all layers)(in the component)
2 Is placing a line/trace on some/all layers below it in the component.
3 If using an autorouter, using a keepout area (defined in the router)

Clearing planes is a different matter. In negative planes a split plane
works ( attempt to tie all the split planes to Ground to avoid any
capacitive effect) and positive, a polygon (not connected).

These cases has more to do with software. Also the need to keep any
signals also has to do with the type of trace that runs below the
crystal (noisy or noise susceptible), the frequency and through hole.
Through hole will radiate, each layer that the hole effects (all).
SMT crystal basically effect that particular layer.

I believe as testing, and documentation increase, we tend to realize all
those things in the dark, aren't really that scary.

Chris Robertson
[log in to unmask] <mailto:[log in to unmask]>

Senior PCB Designer
Lockheed-Martin Services Inc.
4912 Research Dr.
Huntsville, AL 35805
(256) 722-2626
http://www.lmsg.lmco.com <http://www.lmsg.lmco.com/>





Informal Poll:

How many of you prevent traces and clear planes underneath crystals?
I've seen it both ways, and never heard any science one way or
the other.
I've also never heard of any problems with a design that had traces
passing through under the body of a crystal, Have you?

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