>What are you doing as far as via's and conductors under SMD components? I
>noticed the P-Cad lib has keepouts under the chip components. I have been
>routing traces under SMD and have not had any problems.
**
We have not been putting vias under discrete comps. (i.e. chip caps, resistors etc.)
You need to be careful when routing traces under components, you need to allow more clearance to a smd resistor or cap because a trace could be exposed
depending on your soldermask opening.  also I had an occurence where a trace
routed close to a resistor smd pad caused interference.  I would recommend
at least 16 mils clearance minimum (my rule of thumb)
If you can avoid routing under discretes or between smd pads you should.
Always try to maximize clearances wherever possible.
**
>Silk Screen legend sizes seem to be very large on most commercial lib's
>compared to what I have been using. I seem to get away with .008 width and
>sometimes down to .060 height. What is your experience?

**
I've used .050 height, and .008 width minimum.  some places can print it fine, some can't.  **

>I have just finished a Design for a client that demanded that all components
>be orientated in the same direction and also all of them lined up, nice and
>neat.

**
Unfortunately, sometimes a purchasing decision is made by "gee it looks so
pretty"... so I think the circuit functioning is top in priority, but it should look
presentable if possible.
**

>I also was prohibited from putting chip caps on the solder side, even though
>I routinely do it with other designs. Are any of you designing boards that
>are waved with chip caps on the solder side?

**
We are not prohibited from putting caps on the solder side, just not preferable.
If you have a cap and resistor too close together on the back side, they are
different heights and could cause a shadowing effect during wave solder.
Possibly a turbulent wave solder would fix this problem, but you need to make
designs that can be manufactured everywhere today.
**

Karl Bates
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