Tom,
Etchback exposes the cu circuit trace by "etching back" the dielectric inner
layer mtl in a multilayer bd. De-smear only removes the surface layer of
"smeared" mtl formed during the drilling of the hole through the pcb.  Our
experience (as an end user of pcbs) is that etchback is CRITICAL for long term
reliability of higher count multilyr bds (6+).  We specifiy it for ALL
multilyrs. The etchback provides a positive interlock (2-3 point contact) of the
cu trace and the plated cu in the pth. This is required to withstand
differential expansion rates within the pth during T-cycle / shock. The higher
the layer count and thermal excursion, the more important etchback becomes. 

The process is different depending on whether the dielectric is GF of GI. GI
etchback is typically limited to plasma etch, although I believe there is a
chemical (permangenate) process that will go beyond de-smear. GF etchback can be
done chemically.  The plasma process requires capital outlay by the PCB house
... so you must check to see if they are set up to do it if you want etchback.
You can specify it by invoking the 55110 requirements for "positive etchback" on
multilyr pcbs.

Good luck!
Vince Giardini
Proj. Engin, Parker Hannifin Corp.

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When is etchback and/or smear removal applicable?  What is the 
prefered method or required method and how should it be defined
on the drawing for 55110 reqd board?

Appreciate others knowledge, 

Thanks
Tom

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