IPC
Designers Council  Silicon Valley Chapter  MEETING

Date:        
Thursday, July 14th, 2016

Time:        11:30 am - 1:30 pm 

 

Location:

Cadence Design Systems

2655 Seely Ave.  Building 10 

San Jose, CA  95134       

 

Agenda:                                                         

11:30a-11:45a  Arrival - Lunch is Served11:45a-11:55a  Introductions  11:55a-12:10p  Sponsors Spotlight12:10p-1:00p    Speaker Presentation1:00p-1:15p      Q&A1:15p-1:30p      Announcements & Conclusion

 

Please RSVP through EventBrite: July 14 Meeting


 We need headcount
     to order the correct amount of lunches…


 


Speaker: Lee Ritchey - Speeding EdgeTopic: Power Delivery ProblemsAs the electronics industry has migrated to more and more dense electronics operating at higher and higher speeds, two things have happened. 1.       There has been a very rapid shift from wide parallel buses such as PCI and VME to differential serial links.  These differential links are operating at very high speeds. 2.       The above change has result in many fewer nets that must be routed in signal layers and much higher Idd currents along with multiple voltages on the same IC.These changes have shifted the PCB  design problem away from being challenged by huge numbers of nets that must be routed to huge numbers of voltage rails at very high currents.  One of the more recent designs I worked on had 29 different Vdd rails, some with currents approaching 100 amperes.  It took only about two days to arrive at the routing rules and almost a month to properly engineer the power delivery system.This is a paradigm shift in the way PCB design is approached.  This 45 minute presentation will try to describe this problem in detail and offer some solutions along with comparisons of PCB stackups required for each. ~  ~  ~   ~  ~Founder and president of Speeding Edge, Lee Ritchey is considered to be one of the industry´s premier authorities on high-speed PCB and system design. He conducts on-site private training courses for high technology companies and also teaches courses for UC Berkeley´s extension program as well as industry trade shows and technical conferences. In addition, he provides consulting services to top manufacturers of Internet and server products.Ritchey holds a B.S.E.E. degree from California State University, Sacramento where he graduated as outstanding senior. In 1998, he was profiled by EE Times, as "the high-speed design ratchet man".In 2004, Ritchey began contributing a regular column, "PCB Perspectives," which appears once a month in EE Times.

 

 

Please RSVP no later than noon on Tuesday, July 12

I look forward to seeing you there! 
Bob McCreight, C.I.D.Silicon Valley ChapterIPC Designers Council
 		 	   		   		 	   		   		 	   		  

______________________________________________________________________
This email has been scanned by the Symantec Email Security.cloud service.
For more information please contact helpdesk at x2960 or [log in to unmask] 
______________________________________________________________________

---------------------------------------------------------------------------------
DesignerCouncil Mail List provided as a free service by IPC using LISTSERV 16.0.
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF DesignerCouncil.
To temporarily stop/(restart) delivery of DesignerCouncil send: SET DesignerCouncil NOMAIL/(MAIL)
For additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
---------------------------------------------------------------------------------