Hi Fred,
Good questions, I hope you will be able to post the responses you get aside
from responses through the designer's council (like this one). I've been in
the pcb design phase for about 15 years, so I've seen way too much of what goes
on.
> Has anybody been using SMT Plus land patterns? They are advertising a lib.
> for P-Cad. How do they compare to the IPC 782 Patterns?
>
Here at TRW we have implimented the SMT Plus footprints as our standard. When
I first saw the pre-draft of 782A I about croaked. It's no longer a design
standard, it's only a guide (as it implies) and MUST be tailored to your own
practices (fab and assembly issues). We could use it as a standard before the
Rev A as it wasn't a "left-field" all incompassing document.
> What are you doing as far as via's and conductors under SMD components? I
> noticed the P-Cad lib has keepouts under the chip components. I have been
> routing traces under SMD and have not had any problems.
>
Hasn't been a problem with us. 'Course we are not military, and that seems to
be the only case I can think that requires this. It's mostly a concern for
reliability, and whether the pcb is clean under the SMD.
> Has anyone needed to provide a glue dot file for mfg? I noticed that P-Cad
> has that capability but I have never had to provide one in the past. It was
> always created from the placement file.
>
Glue dots are fine, provided it's what your assy house can use and will use.
We don't provide it, because it's really too hard to stay abreast of what our
many assy houses can and can't do, or can do faster with more data. But, that's
not to say if you work with one assy house you couldn't provide them this.
> Silk Screen legend sizes seem to be very large on most commercial lib's
> compared to what I have been using. I seem to get away with .008 width and
> sometimes down to .060 height. What is your experience?
>
Remember, first and foremost, the design lib (like 782A) will first need to be
tailored to suit your needs and requirements BEFORE you use them. .008s and
.060 hts have worked fine for us. As long as you keep in mind what line widths
you use compared with heights you won't get anything you can't read.
> board is finished now but I just know placing the parts for optimal routing
> would have resulted in much shorter runs, and a more functional layout. What
> is your opinion? How are you doing it?
>
TTL boards, this is desireable. For high-speed ECl/MECL boards this practice
will go the wayside. Function will be more important. I don't personally care
for "optimal" placement because it doesn't save me a dime with pick&place. What
does is the type(s) of components you use (dip, SMT or dip/SMT) and placement
design issues (have you considered all mfg requirements and practices?, spacing
reqmts, fine pitch, fiducials, tooling holes, etc.)
> I also was prohibited from putting chip caps on the solder side, even though
> I routinely do it with other designs. Are any of you designing boards that
> are waved with chip caps on the solder side?
>
Chip caps up to and including 1206 size are ok for wave side for our practices,
and we don't put active comps on the wave side, BUT look at commerical boards.
They do most anything. My practice is, if you use a good assy house, they will
do your boards as best as they can to get you the best board possible. If they
feel they can't acheive good solderability with wave on the back side, they
will IR reflow or vapor phase both sides. Done.
It's best to know what your fab and assy houses can and can't do for you, what
input they need from you and how you can tailor that to your requirements.
Enough said.
Good Luck,
Mitch Morey
Sr. PCB Designer
TRW, Inc.
Redondo Beach, CA 90278
Phone: (310)814-5765
Fax: (310)812-4949
EMAIL: [log in to unmask]
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PCB layout is like fine art. You have to DIE to be famous!
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