Thank you, Veronika!

just for the record, I can easily use 12mil in this design,
but other people had advised me to use the full 3.25 mm (>.125 mil)
listed in IPC clearance Table 6-1 and by other online calculators.

thanks to everyone else, too!

still learnin',
Jack



On Fri, Jun 20, 2014 at 4:12 PM, Anderson, Veronika <
[log in to unmask]> wrote:

>  Let’s look at the Material Specification IPC-4101. The requirement 12
> for each FR4 stash sheet is:
>
> Electric strength, minimum (Laminate & prepreg as laminated) is 30kV/mm
> which is approx. 762V/mil.
>
> Taking in account 50% derating, it will be 381V/mil. I use 300V-350V/mil
> as a rule of thumb. That approach allows using a copper with the standard
> profile (vs. low profile) where it is possible.
>
> Therefore the min dielectric thickness in your case is 1700V / 350V per
> mil = 4.86mil. If you are limited to a 4mil dielectric thickness, just have
> your HV traces on each other layer with no copper on adjacent layers.
>
> I had designed a ton of the high voltage boards – this approach had never
> failed. It is better to be safe than sorry, therefore I will not recommend
> 2ply of 1080 in your case. You must provide PCB manufacturer with the
> desired stack-up, therefore the knowledge of the readily available
> materials is essential.
>
>
>
> *Veronika Anderson C.I.D* *| *Sr. Electrical/Mechanical Design Engineer*
> | *Excelitas Technologies
>
>
>
> Office:  +1 626.967.9521 x 236
>
> 1330 East Cypress Street, Covina, CA 91724 USA
>
> [log in to unmask]
>
> www.excelitas.com
>
>
>
>
> > -----Original Message-----
> > From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
> > Jack Olson
> > Sent: Friday, June 20, 2014 7:35 AM
> > To: [log in to unmask]
> > Subject: [DC] z-axis separation for high voltage
> >
> > maybe I'm having a "not enough coffee yet" morning, but I was asked
> > how much separation I need between layers for high voltage.
> >
> > We have a design that may have 1700V in several places.
> > Since we are looking at a clearance into the board, layer-to-layer I'm
> > pretty sure I can use the "internal" column B1 of Table 6-1 in
> > IPC-2221 (using Table 6-1 for z-axis was discussed in a committee
> > meeting and no one
> > disagreed)
> >
> > but the number I get for 1700V is =
> > (.25 mm for the first 500V) plus (.0025 mm for each of the other
> > 1200V, 3
> > mm)
> > equals 3.25 mm
> >
> > For one thing, it already seems like I'm off-track because .25 for
> > 500V doesn't correspond very well with 3 mm for 1200V, but if you
> > can't trust IPC..... well, let's not go there.
> >
> > My REAL question is that, although I'm safe using 3.25 mm, my board is
> > not that thick!
> > Is there a smaller z-axis clearance that can be used for 1700V? across
> > typical FR4 material?
> > (we are using a RoHS compatible 170Tg /126)
> >
> > What's the MINIMUM layer spacing I can use for 1700V?
> >
> > thanks,
> > Jack
> >
> >
>

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