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December 2001

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Subject:
From:
Tom Monico <[log in to unmask]>
Reply To:
Tom Monico <[log in to unmask]>
Date:
Fri, 21 Dec 2001 20:23:18 -0500
Content-Type:
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text/plain (86 lines)
Stacy,

This does not address your specific question, but check out KwickFit from
MicroMega solutions. It can help you calculate array designs that provide
the highest part per panel yield for any panel size used by a manufacturer.

Go to www.micromeg.com

Tom




----- Original Message -----
From: "My Nguyen" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, December 21, 2001 12:34 PM
Subject: [DC] Panel Layout Standardization


> Hello Technetters and Designers,
>
> First of all MERRY CHRISTMAS!
>
> I am working on Panel Layout Standardization project.
> We make memory (SIMM,DIMM,DDR,RIMM,SODIMM,CF, etc)
> However, to better pursue the upper manager to see the
> potential benefit from doing this, I have to make a
> presentation in which all the ideas, objects, goals,
> have to be presented clearly.
>
> I have seen many, however, there are always more
> upside and downside of the Panel Layout Standadization
> that I have not seen.  I NEED YOUR HELP HERE.
>
> 1. Universally, I know the boardhouse use 18x24
> rawstock size.  However, besides it, what else do they
> use (Taiwan, Korean, Chinese, Ireland, and USA).
> 2. However the X-Out affects the cost of making PCB?
> (We want panel size are around of 12' - L x 7' - W in
> which the maximum of PCB can possibly fit).
> 3. Screen Printing quality of those big panel vs.
> smaller panel.
> 4. More!
>
> Please advise me.
> Thanks!
> Again Merry Christmas!!!
>
> Stacy
>
>
> __________________________________________________
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>
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