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January 2005

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Subject:
From:
"Brooks,Bill" <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Wed, 5 Jan 2005 17:33:31 -0800
Content-Type:
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text/plain (366 lines)
Thanks for the advice... all of you.

That's exactly what I did Lou, I got a list of other parts compared them and
we talked a compromise...  The board thickness needs to be .062 like the
other boards in the project, (that would give us an aspect ratio issue with
any through-hole microvias) and the boards fit into an old fashioned card
cage arrangement kind of like the old S-100 bus construction if anyone
remembers that technology...  They are not tight designs, we have plenty of
real estate, and of course why make it expensive if you can avoid it... So I
think we satisfactorily justified not going down that path to the very small
scale integration.

You see, the problem we are faced with, because of the chip markets being
driven by volume purchasers (like the cell phone industry)... older
technology product is more and more challenged to find parts.  We either get
creative with the solutions to finding unavailable parts or we have to
completely redesign the product with newer parts. Naturally the company
wants to get as much life out of the existing product as they can, their
customers still want to purchase it and if we can get the parts we can make
money without having to incur redevelopment costs. Product life extension is
necessary in our markets... so that's the game we play here.

At any rate, the IC will be in the PQFP package on this go around... (darn)
but it's the best solution and makes the most sense. Since we have the room
they are going to use some PLCC packages for some of the IC's as well
because they are readily available and more robust.

Thanks again for your help... :)

Best regards,

Bill Brooks - KG6VVP
PCB Design Engineer , C.I.D.+, C.I.I.
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
e-mail:[log in to unmask]
http://www.dtwc.com
http://pcbwizards.com


-----Original Message-----
From: Louis Dallara [mailto:[log in to unmask]]
Sent: Wednesday, January 05, 2005 4:55 PM
To: [log in to unmask]
Subject: Re: [DC] Fine pitch parts... 0.5mm pitch BGA or .05mm pitch PQFP

IMHO;
I'd look at what the other package types are on the board and match
acording to pitch.
I would not like to have just one super fine pitch bga. (ie .05mm pitch
part)

Lou Dallara

Denis Lefebvre wrote:

>I'd opt for the QFP
>
>-----Original Message-----
>From: Brooks,Bill [mailto:[log in to unmask]]
>Sent: Wednesday, January 05, 2005 9:55 AM
>To: [log in to unmask]
>Subject: [DC] Fine pitch parts... 0.5mm pitch BGA or .05mm pitch PQFP
>
>
>Hi again...
>
>I am faced with a decision to make...
>We have a need to use a Codec on a design I'm doing and it comes in 2
>'flavors' of packaging styles...
>
>One is a MicroStar BGA package with a 5mm chip body and 0.5mm pitch ball
>contacts in a 9X9 array....
>
>The other is a 48 pin PQFP with 5.5mm body and 0.5mm pitch gull wing
>contacts on 4 sides.
>
>I think we have done the 0.5mm pitch gullwing devices here before. We were
>using a Flash memory chip with that pitch... However the smallest pitch we
>have done here with a BGA is 0.8mm.
>
>Are there any issues that you have seen with the 0.5mm BGA that would make
>you prefer the gull wing leads over it?
>
>I know the via breakout on the 0.8mm pitch BGA was a little difficult and
>required very small drilled vias to get the signals out... Will I be forced
>to use laser drilled vias to use the 0.5mm pitch BGA?
>
>Any advice is most welcome...
>
>Thanks in advance...
>
>Bill Brooks - KG6VVP
>PCB Design Engineer , C.I.D.+, C.I.I.
>Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
>e-mail:[log in to unmask]
>http://www.dtwc.com
>http://pcbwizards.com
>
>
>-----Original Message-----
>From: Brooks,Bill [mailto:[log in to unmask]]
>Sent: Tuesday, January 04, 2005 9:35 AM
>To: [log in to unmask]
>Subject: Re: [DC] Assembly panels
>
>VERY GOOD POINTS CHRIS! (and a nice way to deal with the vendor mistake
>issues)
>
>In our case, we have a depanelizing tool, or singulation tool as you would
>say, (my spell checker 'hates' both of those words...) and it is important
>that the clearance between tie points or web points or singulation points
>be sufficient to allow the tool access to cut out the web. IF the board
>manufacturer moves them to their preference they can make it near
impossible
>to use our equipment to de-panel the boards.
>
>I have a 'web detail' on my drawings that specifies the structure of the
web
>it's tolerances and locations are clearly shown to avoid confusion... Our
>old designs had nothing more than a note, "add 2 ties per side" or
something
>like that and a picture of the rough layout of the panel. Well we have had
>one vendor make the panel one way, and on a separate order later from
>another vendor they did it a different way, and then a third vendor would
do
>it their way... too much not specified... So we wrote an ECO to the drawing
>and added the details to specify the exact locations and web details to
>avoid variances from vendor to vendor and consistent tooling to avoid
>additional costs of making new past screens and updating pick and place
>programs etc... Fixed In-Circuit-Test fixtures would wreak havoc on us if
we
>had them on a board panel and had some well meaning board manufacturer
shift
>the board array pattern on us. I can imagine that some of us have never had
>these problems, not all designers have the same criteria to design to, but
>those who mass produce and are dealing with product configuration
management
>issues are really sensitive to these issues because they can cost so much
>money when ignored.
>
>Great conversation topic guys...
>
>Best regards,
>
>
>Bill Brooks - KG6VVP
>PCB Design Engineer , C.I.D.+, C.I.I.
>Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
>e-mail:[log in to unmask]
>http://www.dtwc.com
>http://pcbwizards.com
>
>-----Original Message-----
>From: Chris Ball [mailto:[log in to unmask]]
>Sent: Tuesday, January 04, 2005 5:35 AM
>To: [log in to unmask]
>Subject: Re: [DC] Assembly panels
>
>Hi Ted-
>
>My $0.02:
>
>If you located the singulation points to avoid stressing components when
>separating the individual boards, and they have changed these locations,
>you have a problem.
>
>If ICT fixtures, solder paste screens, etc., have been tooled per your
>original array drawing, you have a problem.
>
>The fact that they made changes without communicating is a problem, but is
>probably not insurmountable, if you are willing to change your
>documentation and have their assurance that they won't do this sort of
>thing again without you prior approval.
>
>If you submit a complete drawing package with the job, they should submit a
>request for change, which can be evaluated and complied with, or not, per
>the merits of their request vs. your original intentions.
>
>Happy New Year!
>-Chris
>
>P.S. The IPC guideline is just that; a guideline. Variance from it is no
>problem if justified.
>
>
>
>
>
>                       Ted Tontis
>                       <[log in to unmask]>           To:
>[log in to unmask]
>                       Sent by: DesignerCouncil          cc:
>                       <[log in to unmask]>         Subject:    [DC]
>Assembly panels
>
>                       12/29/2004 12:17 PM
>                       Please respond to
>                       "(Designers Council
>                       Forum)"; Please respond to
>                       Ted Tontis
>
>
>
>
>
>
>
>The data package that I sent to our assembly house was in a three board
>assembly panel. I used the IPC standard for choosing the size of the panel.
>It was a panel 260mm x 180mm containing three boards. I talked to the
>assembly house yesterday and was notified that the assembly panel size was
>changed. There are still three boards in the panel, however the bare board
>manufacture decreased the size of the assembly panel. First question I have
>is per IPC-2221 5.2.2 Figure 5-1 I picked the correct size for the panel,
>optimizing the manufacturing panel? The second question is that in my notes
>"no changes where to be made to the board without first receiving written
>permission of us." This now leaves me with a question mark over my head
>what else was changed without me knowing it. Should I confront the Assembly
>house for not following my notes? Have other designers faced similar
>problems and what was your course of action?
>
>Regards,
>
>Ted Tontis CID
>Engage Networks Inc.
>1320 N. Dr. Martin Luther King Drive
>River Level
>Milwaukee, WI 53212
>PH 414-918-4267
>FX 414-273-7601
>
>
>
>
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