Bill,
I bet your PCB has SMA connectors. What's more, measure the trace width from
that connector, and I'll bet it's very close to 70 mils wide. That's 50 ohms
for a FR4 material, stripline. This may not be the best way to construct the
PCB, but if it was just designed to be a prototype, it was probably good
enough. If this is the case, the only way to reduce the thickness of the RF
layer pair, and better balance the construction, is to reduce the trace
width, with the limiting factors maybe being max current, but probably is
based on component size.
David Ricketts
Pertek Engineering
Voice: 949-475-4485
Fax: 949-475-4493
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]]On Behalf Of
Brooks,Bill
Sent: Monday, June 24, 2002 3:32 PM
To: [log in to unmask]
Subject: [DC] Board Layer Stack up Guidelines
Hi folks,
I have a older proto board (an IF Demodulator) that was defined with an
asymmetrical stack up and I am concerned about the cost issues with leaving
it alone... Since we are changing the board at this time, I thought to check
for any issues with the design package and found this anomaly...
It looks like this:
.063 overall thick FR4 material
0.070 max ________________________ Top Layer Signal
.032 separation--->________________________ GND Plane
________________________ Internal Signal
0.00 ________________________ Bottom layer Signal
The odd part being, the forced separation between the ground plane and the
top signal layer where the RF components reside, primarily. Have you had any
experience with this sort of thing? Is there a good reference I can refer to
that deals with Board stack up issues?
Do you think the board is at risk for flatness problems?
The EE assures me that he knows of no known issues with the electrical
properties of the circuit that would require a stack up of that sort. He
says the only reason he can think of was parasitics and/or shielding.
Like to hear your thoughts....
- Bill Brooks
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