That most likely will not happen, the JTAG code in the chips is not a
constant thing that tests the same pins for all devices. It will always
require collaboration with the Test engineer, the Design Engineer, and
you.
Applying a "NO_TEST" property in the schematic to nets that don't
require testing is probably as close as you'll get to that, and most
engineers are not going to have the time to "waste" on that :)
--
George Patrick
Tektronix, Inc.
Central Engineering, EDS Applications Support
P.O. Box 500, M/S 39-512
Beaverton, OR 97077-0001
* 503-627-5272 (voice) * 503-627-5587 (fax)
http://www.tektronix.com http://www.pcb-designer.com
"Off-Grid and Proud of it!"
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Karl
Bates
Sent: Wednesday, June 06, 2007 14:01
To: [log in to unmask]
Subject: Re: [DC] ICT, bed-of-nails and CAD tool support?
What I would really like to see would be the full scale integration of
all
techniques of testing. For example on some of the really difficult
designs
a lot of the PCB can be tested with JTAG, necessitating only adding test
points that are not JTAG'able. (note new PCB'onics words).
I'm sure there are situations where a functional test would test most of
the
circuit, and again combining other test points and JTAG it could be a
100%
test. It is quickly becoming a problem with designs !
Karl
From: "Wolfe, Robert" <[log in to unmask]>
Reply-To: "(Designers Council Forum)" <[log in to unmask]>,
"Wolfe, Robert" <[log in to unmask]>
To: [log in to unmask]
Subject: Re: [DC] ICT, bed-of-nails and CAD tool support?
Date: Wed, 6 Jun 2007 16:36:20 -0400
Bill,
In the past few years I've been involved in designs from zero test
coverage required up to the 100% test coverage required. Yes as far as
probe type testing goes yes with very dense design requirements allowing
room for even
30 mil pads can sometime be a challenge.
I've been using both Mentor Expedition & the Altium product. I'll admit
Expedition is a bit more sophisticated in the process of test points but
Both have the ability to automate the process reasonably well. Of course
with some upfront planning.
In the case where people use actual parts on the schematic to define
test points (and I did that too back in the day on Cadnetix) yes you
will not
get basically a true test point report out of the system, because
naturally
the system didn't assign these as test points, but you need to think of
getting the info you need from assembly outputs instead like pick&place
files you can then separate out just the test point data.
One problem I see with all systems (using any kind of autorouting) or
for that matter really hand routing too. I have not seen a system yet
that
as you are routing and placing vias the system will only place the one
test point needed per net than move on to all other places with standard
via.
Set routing rules and test point rules and as you are routing only put
the required down and leave the rest of the net to routing rules.
It really is a route it then see how many the system can assign, then
set closer rules find some more then ultimately have to place a few by
hand. You don't really want the entire design spaced out so every via is
a valid test point site, yet you really have to do some degree to get
the system to obtain 100% coverage in a first pass attempt. So that
really becomes
the balancing act on routing rules vs leaving room for test points.
Bob
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
Brooks,Bill
Sent: Tuesday, June 05, 2007 8:16 PM
To: [log in to unmask]
Subject: [DC] ICT, bed-of-nails and CAD tool support?
'In-Circuit Test' is a seldom discussed subject at the 'designer's round
table' here...
I'm curious how other designers are affected by test points and how they
deal with testability in their designs.
I have placed test points in schematics and treated them as 'components'
on
the board before...
What have you seen for test point support from the CAD vendors and is
there
an easy way to automate this?
Also those who have to test for a living... what is the process you use
and
are the outputs from these CAD tools any help?
Best regards,
Bill Brooks, CID+
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