Barbara J. Burcham, C.I.D.
Fairfield Industries, Inc
281-275-7687
[log in to unmask]
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
Brooks,Bill
Sent: Wednesday, June 09, 2004 12:43 PM
To: [log in to unmask]
Subject: [DC] PCB EDA survey... ?
Quoted from an article I just read in a 'Planet Analog' Newsletter...
Authored by Mike Santarini, EE Times
---------------------
SAN JOSE, Calif. " Mentor Graphics and Cadence Design Systems took the
lion's share of top honors in a PCB EDA survey, but Agilent EEsof
garnered
the top spot in customer satisfaction.
The 2004 study commissioned by EE Times gathered data for three studies:
an
IC EDA study, this PCB study and for the first time a study on FPGA EDA
tool
usage. Separate summaries of the FPGA and EDA studies can be found on
eeDesign.
The "2004 board study" drew 628 respondents, including 436 from North
America and 192 from Europe. Fifty-five percent of respondents
identified
themselves as design engineers, 27 percent as engineering management, 6
percent as general management, 4 percent as layout engineer, 1 percent
as
CAD manager and 8 percent as "other."
Ninety percent of respondents said they are involved with PCB design
while
the rest are involved in layout.
Respondents said they build boards for a wide variety of applications.
But
the bulk of respondents create boards for: the industrial control, test
and
measurement market; the consumer and automotive markets; communications
equipment makers; and for military and aerospace.
The study found that the average size of a PCB design team is four
engineers, one more than the average in last year's study.
Seventy percent of respondents said PCB projects are completed in three
months or less, 23 percent said they complete them in 4-6 months, 4
percent
complete them in seven to 11 months, while 3 percent said their PCB
designs
take "one to three years or more to complete." The median of eight
months to
complete a PCB design did not change year over year.
Respondents said that 30 percent of overall design time is spent on
schematic entry, 31 percent on PCB layout, 20 percent on test and
manufacturing support, 11 percent on signal integrity analysis and 8
percent
on "thermal/EMI analysis."
The study indicates on average there are three PCBs in each system
design,
with on average one FPGA and one ASIC per PCB.
North American PCB designs averaged seven layers, while European PCB
designs
averaged five, according to the study. Average clock speeds for designs
was
125 MHz, up from an average of 93 MHz in 2003.
On average, 16 percent of the networks in a PCB design were considered
"high-speed."
Fifty percent said they plan on engaging in the same number of PCB
design
starts in 2004 as they did in 2003, 20 percent said "more," 14 percent
said
"much more" while 7 percent indicated there will be "less" and nine
percent
"much less" than last year.
Forty-nine percent of PCB respondents indicated that their tool budgets
will
be the same in 2004 as in 2003. Twenty percent said they plan to spend
more
this year, and 15 percent said they plan on spending "much more" this
year.
Nine percent indicated they would spend less than last year on tools and
7
percent said they would spend much less on tools than they did last
year.
Sixty-three percent of respondents identified signal integrity as a
"very
critical" issue in PCB design.
Among vendors, Agilent EEsof rated the highest in customer satisfaction
with
79 percent of EEsof users surveyed indicating they were either "very" or
"somewhat" satisfied with EEsof tools.
Mentor ranked second with a 75 percent approval rating followed closely
by
Cadence with a 71 percent satisfaction rating. The industry average was
65
percent, according to the study.
Mentor Graphics took top honors in several categories including: best
after-sales support, best documentation, most ethical company, best
integration with other vendors' tools, knowledgeable sales reps and best
training services.
Cadence finished first as: current technology leader, technology leader
in
three years and clearest vision of the future, among others offers.
Meanwhile Cadence spin out OrCAD, which is now largely under the control
of
a distributor, also garnered several top honors, including competitive
pricing, vendor familiarity, product association, purchase consideration
and
product usage."
-----------------------------------
Now, does this data look strange to anyone? Maybe a little skewed?
Maybe it's just me... but nobody gives me 3 to 8 months to complete a
board... how about you?
Of course I don't use Mentor now or Cadence, I use Protel daily. But do
you
agree that their findings are ordinary or odd? And what about the 25
percent that did not feel they were satisfied with the tool? I wonder
why?
Let's ask the same questions of our member constituents... If you can
spend
a few minutes answer the following questions and see how it stacks up
with
their survey... this should be fun.
1) What is your Job title?
Sr. PCB Designer
2) Are you involved in PCB Design or some other activity - (please
indicate)
PCB Design
3) What type of boards do you create?
Boards for seismic data acquisition
4) How large is a typical design team at your company?
2-3. The desing engineer, me, and maybe another engineer for
design review
5) What is the duration of your typical design time?
This is, off course, dependent on size and complexity. Anywhere
from 3 days to 6 weeks.
6) What percentage of the time spent is on Schematic Development?
5% I receive completed schematics, my task is to add footprint
library information for successful packaging.
7) What percentage of the time spent is on PCB Design or Layout
85%
8) What percentage of the time spent is on Manufacturing support
5%
9) What percentage of the time spent is on Signal Integrity analysis
5%
10) What percentage of the time spent is on Thermal/EMI
1%
11) How many boards are typically in your projects?
5
12) How many FPGA's or ASIC's are used in your projects?
Multiple FPGA's and BGA's on each board
13) What is the average layer count of your PCB designs
6 - 8
14) What is the typical clock speed or frequency your designs operate
at?
1 Mhz
15) Do you consider your designs to be 'high speed'?
No...only some functions.
16) Will you be doing much more, more, the same, less, or much less
designs
next year?
The same
17) What CAD tool(s) do you use?
OrCAD
18) Do you plan on spending more, same or less on CAD tools next year?
Same
19) Are Signal Integrity tools important to the success of your board
designs?
No
20) Are you very satisfied, satisfied, or not satisfied with your design
tools?
Satisfied
21) What does your CAD tool do Right? Or Wrong? What do you like about
it
and not like about it.
Great Post Processing tool, good customer support.
Every new release has a new set of bugs that I have to discover
and figure out how to work around. I am tired of that.
This should be interesting.... let us know how you stack up against the
EDA
survey... similar or different?
Enjoy.
Bill Brooks
PCB Design Engineer , C.I.D., C.I.I.
Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510
http://pcbwizards.com
------------------------------------------------------------------------
---------
DesignerCouncil Mail List provided as a free service by IPC using
LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text
in
the BODY (NOT the subject field): SIGNOFF DesignerCouncil.
To set a vacation stop for delivery of DesignerCouncil send: SET
DesignerCouncil NOMAIL
Search previous postings at: www.ipc.org > On-Line Resources & Databases
> E-mail Archives
Please visit IPC web site
http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional
information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
------------------------------------------------------------------------
---------
---------------------------------------------------------------------------------
DesignerCouncil Mail List provided as a free service by IPC using LISTSERV 1.8d
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field): SIGNOFF DesignerCouncil.
To set a vacation stop for delivery of DesignerCouncil send: SET DesignerCouncil NOMAIL
Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
---------------------------------------------------------------------------------
|
