As a result of some discussion with our in-house manufacturing,
we decided to re-evaluate our minimum via size for .093 board thickness.
Just for fun (grin) I decided to look everything up in the latest IPC specs.

If anyone enjoys poking holes in IPC logic, here is the result:
(see below for supporting references)

calculated IPC minimum via size = 19.7 mil drill with 41.4 mil land

Can anyone think of a way to design PCBs to meet IPC with a smaller via?

-=-=-

Our initial parameters are:
Design for Class 2 (no one is going to die if the product fails)
Assume Level C producibility but prefer Level B (ha!)
Many designs are >12" long
Many designs are >8 layers

According to IPC-2222 Table 9-6,
a plated through via on a board >2mm thick for Class 2  is .5mm minimum
Result: the minimum drill size is 19.68mils

According to IPC-2221 Table 9-1,
For a Level C board up to 450mm dimension (<18inches)
and with note 2 to add .05mm to .45mm for >8 layers is .5mm minimum
Result: Minimum Fabrication Tolerance is 19.68mils

According to IPC-2222 Paragraph 9.1.1
minimum land = a + 2b + c
where
a = maximum drill diameter (19.68mils)
b = minimum annular ring (1mil)
c = fabrication allowance (19.68mils)
Result: minimum land diameter is 41.37mils

A 20 mil hole with a 42 mil pad is difficult to design with.
To meet IPC even at Level C, the only thing I can see to reduce is
the minimum annular ring to allow breakout, are ya kiddin me?
Am I missing something?

Any comments are greatly appreciated!

Jack

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