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June 2002

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Subject:
From:
DUTTON Phil <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Tue, 25 Jun 2002 12:19:44 +1000
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Hello Bill,

Just trying to help clear your muddy waters...
Your 10mil tracks on this stackup will give you approx 107 ohms
characteristic impedance. This is comparable to the characteristic
impedance of many 0.050" pitch ribbon cables.
(I've recently designed a board that had this as a consideration)
Any missmatch will affect RF (even puttering along in the MHz regions)
May be just a coincidence. Perhaps all of the RF circuitry is on L1,
with some control circuitry on L3 & L4?
The gnd plane providing a reference plane for L1, and helping shield the
signals on L3 & L4.
With the plane pretty well central in the board, chances of warping due
to assymettric build may not be a problem.

regards,

Phil Dutton C.I.D.



-----Original Message-----
From: Brooks,Bill [mailto:[log in to unmask]]
Sent: Tuesday, 25 June 2002 09:57
To: [log in to unmask]
Subject: Re: [DC] Board Layer Stack up Guidelines


Thanks Dave!  I can see you know about RF... :)

The weird thing about this board is it's constructed with 10 mil lines
and
the power is distributed with 25 mil lines.... There are no SMA's on the
board. There are, however a couple of OSMT's that are used for test. The
Local Oscillator is running at 20MHz and the only plane is the ground
plane
which is basically centered in the layer stack with the other 2 signal
layers, number 3 and 4, compacted together in the other half of the
board
layer stack. The signals are coming onto the board in a ribbon cable and
exiting in ribbon cables... I have a hard time believing that this board
is
a matched impedance assembly, because the cables tell me it can't be.
(Also
the EE said there was no need for a matched impedance on this assembly)
The components are almost all surface mount. It is used in a VHF radio
for
IF demodulation. But this is fairly LOW freq. design. ( I have worked
with
circuits that are in the 15Ghz range before)

Good reasoning though, I would have thought the same given the same
info...
I apologize for not telling enough about the problem to give you a
better
picture... perhaps this will muddy the water further rather than making
it
clearer... :)

- Bill Brooks


-----Original Message-----
From: David Ricketts [mailto:[log in to unmask]]
Sent: Monday, June 24, 2002 5:12 PM
To: (Designers Council Forum); Brooks,Bill
Subject: RE: [DC] Board Layer Stack up Guidelines

Bill,

I bet your PCB has SMA connectors. What's more, measure the trace width
from
that connector, and I'll bet it's very close to 70 mils wide. That's 50
ohms
for a FR4 material, stripline. This may not be the best way to construct
the
PCB, but if it was just designed to be a prototype, it was probably good
enough. If this is the case, the only way to reduce the thickness of the
RF
layer pair, and better balance the construction, is to reduce the trace
width, with the limiting factors maybe being max current, but probably
is
based on component size.

David Ricketts

Pertek Engineering
Voice: 949-475-4485
Fax:   949-475-4493

-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]]On Behalf Of
Brooks,Bill
Sent: Monday, June 24, 2002 3:32 PM
To: [log in to unmask]
Subject: [DC] Board Layer Stack up Guidelines


Hi folks,
I have a older proto board (an IF Demodulator) that was defined with an
asymmetrical stack up and I am concerned about the cost issues with
leaving
it alone... Since we are changing the board at this time, I thought to
check
for any issues with the design package and found this anomaly...

It looks like this:
.063 overall thick FR4 material

     0.070 max     ________________________ Top Layer Signal
.032 separation--->________________________ GND Plane
                   ________________________ Internal Signal
   0.00            ________________________ Bottom layer Signal

The odd part being, the forced separation between the ground plane and
the
top signal layer where the RF components reside, primarily. Have you had
any
experience with this sort of thing? Is there a good reference I can
refer to
that deals with Board stack up issues?
Do you think the board is at risk for flatness problems?
The EE assures me that he knows of no known issues with the electrical
properties of the circuit that would require a stack up of that sort. He
says the only reason he can think of was parasitics and/or shielding.
Like to hear your thoughts....

- Bill Brooks

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