Silicon Valley Chapter of the IPC Designers Council
Our next meeting will take place on Tuesday, January 9, 2007.

Location:
Mentor Graphics
1001 Ridder Park Drive, San Jose, CA
Tuesday, January 9, 2007
Time: 11:30AM - 1:30PM
$1 for chapter members; $5 for visitors
DOOR PRIZE: $25 IPC Publication Certificate

RSVP required > send to [log in to unmask]

  Topic: Layout effects on signal integrity
I am planning to talk about crosstalk, push-in push out effects in stripline and mircostrip (similar to the article), SMA launch optimization, end to end channel and the effects of individual pieces, via effects in the time domain. I will present mostly simulation data.
"From article reference: "
http://www.pldesignline.com/howto/showArticle.jhtml?articleId=188103193&pgno=2

Speaker:
Suresh Subramaniam is a Member of Technical Staff at CSwitch Corporation (www.cswitch.com) where he is currently involved in package design and signal integrity simulations. Piror to that he spent more than seven years at Xilinx in various roles ranging from FPGA performance characterization, and signal integrity modeling and design of a number of high speed reference boards (10 Gbps transceivers). He earned his Ph.D in Computational and Cognitive Neurosciences and his MS in Electrical Engineering (VLSI) from the University of Southern California, Los Angeles.

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  RSVP is required by 4PM Monday (1/8/07) > send to [log in to unmask]

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