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September 2007

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Subject:
From:
Charles Gervasi <[log in to unmask]>
Reply To:
(Designers Council Forum)
Date:
Thu, 27 Sep 2007 06:43:41 -0700
Content-Type:
text/plain
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I am coming from the EE side and am notorious for changing the design
several times during the course of the layout.  

When I do this I try to document in e-mail that I initiated out of scope
changes that will increase the cost and possibly make the schedule slip.
This makes it hard for designers to schedule new projects after mine
because they never know how long it's going to take.  But I really
appreciate designers who are willing to do work and then tear up parts
of it as changes come in.  

I do some layouts myself.  So I know that pain involved in working
carefully on something for days and then deleting it and starting over.


If the design cycle went ideally: complete schematic, design review,
everyone signs off on placement, begin routing; then we could hand the
layout to the cheapest board designer on earth.  Instead we pay more and
receive more work-in-progress trial-and-error board design.

I hope no one has ever felt like the fall guy for schedule and budget
overruns due to my in-progress design changes.  

-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
carlos mossin
Sent: Wednesday, September 26, 2007 7:04 PM
To: [log in to unmask]
Subject: Re: [DC] Conversation topic: Getting your designs done right!

Hi Bill:

This is my number one all time pet peeve.
  A project goes to PCB layout before the schematic is  100% complete.
Or
has even been to a design review.  Management thinks that the PCB
designer
can at least get started on the project and work concurrently with the
the
Design Eng.   What ends up happenning is 20-30 netlists revisions later,
I
may have all the info and a complete netlist imported.
Unfortunately for the PCB designer, the meter started running the moment
the
first netlist was produced.  the endless cycle of "Churn" as I call it
creates an environment where the PCB designer does not want to actually
go
forward with the netlist at hand since he/she is aware its going to
change
at anytime.  This then leaves the PCB designer with typically 3-4 days
left
in his alotted time scheduled to finish the entire design.  Most often
the
design eng. does not want to fess up to management that they made
changes to
the design and have eaten up 2 weeks of the 3 weeks that where alloted
for
the PCB layout.
 I have since required that during the input review meeting, management
show
that the schematic has been reviewed and is ready to go. Of course last
minute changes are inevitable. This has earned me the label of "Hardass"

Anybody have a better sollution?

carlos CID

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