At 11:46 AM 10/20/99 EDT, [log in to unmask] wrote:
>Hi,  I hope someone can help me out here.  I'm looking for suggestions on
>ways to quite down traces that we know are going to be noise generators.  If
>using a 6 layer board...what is the best stack up?  Should power and ground
>planes always be kept next to each other for optimum capacitive performance?
>Which layer should these noisy lines be kept on?  Any help?

I think I would agree with another writer that using layers 2 and 5 for
power and ground and putting the noise traces on 3 and 4 is probably the
safest idea; certainly if radiated noise is the concern. But that is not
the end of the story.

If traces change from, say, layer 2 to 4 or 6, the return current -- or
most of it -- will ideally change from 2 to 5. To be able to do this
without substantially increasing the loop area, there must be good
capacitative coupling between layers 2 and 5. This means that bypass
capacitors should be distributed liberally, and the length of the trace
between the via and the pad of the cap should be kept to a minimum. I'd
really like to see the via be in the pad, but for the assembly problems
this can create. Also it is desireable, in general, to use smaller rather
than larger capacitor packages, such as 0603 instead of 0805, to keep
package inductance to a minimum.

One should also, of course, observe good layer bias so that, in general,
traces do not parallel each other with nothing but a thin piece prepreg in
between, and the farther apart the traces are, the better the isolation.

I'm not an RF engineer, so I don't want to say what is the best reference,
but I will mention that recently when I was asked if I was competent for
high-speed design, it did not hurt at all that I mentioned I had been
reading High-Speed Digital Design, A Handbook of Black Magic, by Howard
Johnson and Martin Graham, which I had bought a few months before from
amazon.com.

I lot of practices that we used for years, thinking they were good or at
least not harmful, turn out to be not so great as edge rates increase.

One of the jobs I did for the company that asked me involved redoing the
work of another designer who insisted on running stringers to bypass caps
instead of simply dropping a via immediately next to the cap to a power
plane. He thought he was doing it right by making a direct path from the
power pins to the associated bypass cap. But connecting the power pins
directly to the plane and likewise the bypass caps is far more effective,
it appears, taking better advantage of the distributed capacitance of the
planes.

In spite of what I wrote about about the stackup, it is conceivable that
having power as 3 and 4 will be more effective; not enough information was
provided to give a definitive answer, and it is not necessarily simple....
On a board with components on both sides, if it can be implemented in 6
layers, having 3/4 as power planes can be quite effective; the impedance of
the traces on 2/5 can be a reasonable number, say 50 ohms (embedded
microstrip), with 7 mil traces on 25 mil pitch.

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Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433