Hi Mark,

Haven't relieved them in ages. As far as I know all my boards have been
working (more often they've been shelfed per market changes....:) Think
of it Mark, a via is only plated, it's not soldered to. You solder to
component pads. This is not the case with vias. The only time I might
relieve a via is if it was greater than say .040" (power connections on
RF boards), but then maybe not...

Why would a non-relieved via have more reliability problems? It's tied
to the copper plane all the way around, by way of plating. Would a
relieved via (with only four little tie areas connected) be more
reliable? I personally don't think so.

When all else fails, ask your board house. Have one of their
manufacturing engineers explain it.

Best of times...

Mitch
Sr PCB Designer
San Diego, CA

---------Included Message----------
>      Date: Tue, 12 Dec 2000 09:23:12 -0800
>      From: "Mark Gutierrez" <[log in to unmask]>
>      Reply-To: "DesignerCouncil E-Mail Forum."
<[log in to unmask]>, "Mark Gutierrez" <[log in to unmask]>
>      To: <[log in to unmask]>
>      Subject: [DC] Thermal relief for Vias?
>
>      Someone here suggested that all vias connected to power and
ground planes
>      should have the thermal relief's eliminated. Reason to
>      minimize inductance to power planes. I recall reading somewhere
about
>      removing thermals could induce reliability problems. Can anyone
share their
>      knowledge and experience with this?. IPC-2221 specifies thermal
relief is
>      only required for holes that are subject to soldering in large
conductor
>      areas. Wouldn't this apply to a via tied to a plane coming off a
SMD land?
>
>      Mark Gutierrez
>
>
>      Mark Gutierrez
>
>      Senior Printed Circuit Designer
>
>      Blaze Network Products Inc.
>
>      5180 Hacienda Drive
>
>      Dublin, CA 94568
>
>      email: [log in to unmask] <mailto:[log in to unmask]>
>
>      www.blazenp.com <http://www.blazenp.com/>
>
>
>
>
>
---------End of Included Message----------
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