Thanks for your info Ray, but I haven't had a fabricator explain that
issue to me yet, and I'm not aware of any of my boards failing over the
years, 'course I don't do military/space application boards, so I don't
worry about stress testing the boards. I think the industry is well
matured to put out quality product, and my current PC boards all utilize
plated shut vias. I have heard you arguement before though. :)
Mitch
---------Included Message----------
> Date: Thu, 30 Mar 2000 11:57:57 -0800
> From: "Ray Humphrey" <[log in to unmask]>
> Reply-To: "Ray Humphrey" <[log in to unmask]>
> To: "DesignerCouncil E-Mail Forum." <[log in to unmask]>,
<[log in to unmask]>
> Subject: RE: [DC] signal via padstacks
>
> Mitch,
> I would disagree with the idea of -.013 tolerance on a .013 hole.
Plating a
> hole shut allows for the possibility of trapping contaminants
inside the
> barrel, which can leach and/or cause cracking of the barrel
during wave
> soldering, due to pressure build-up. Hole barrels plate from the
outside to
> the inside, sometimes leaving a void in the middle. A better
approach is to
> specify a tolerance of -.008, still giving the fabricator plenty
of room
> with no possibility of a trapping problem. (I use a .025 pad
with a .012,
> +.003/-.009 hole.)
>
> Ray
>
>
> -----Original Message-----
> From: DesignerCouncil [mailto:[log in to unmask]]On Behalf
Of Mitch
> Morey
> Sent: Thursday, March 30, 2000 10:43 AM
> To: [log in to unmask]
> Subject: Re: [DC] signal via padstacks
>
>
> Hi Tom,
>
> I don't have a problem with what your predecessors did in the
past. Seen
> it many times so far. One suggestion I might make is to increase
your
> tolerance range on the .013" finished holes to be +.003/-.013
That
> would allow the fabrciators to do a couple things. 1) They could
plate
> the vias shut, assuring them the .001 plating required; or 2) to
use a
> smaller drill to meet the application. Either way, it's a sure
win for
> you, and will make the fab house happier, especially if your
boards are
> very dense. But, for .062 boards, what you've used in the past
still
> sounds plenty reasonable to me. Heck, I've seen a .096" board
with .015"
> finished holes with .025" pads! Did it work? Yup, 'cuz they also
spec'd
> +.003/-.015" finshed tolerance. :)
>
> Good luck.
>
> Mitch
> Sr PCB Designer
> San Diego, CA
>
> ---------Included Message----------
> > Date: Thu, 30 Mar 2000 09:18:52 -0500
> > From: "Frayda, Tom" <[log in to unmask]>
> > Reply-To: "DesignerCouncil E-Mail Forum."
> <[log in to unmask]>, "Frayda, Tom"
<[log in to unmask]>
> > To: <[log in to unmask]>
> > Subject: [DC] signal via padstacks
> >
> >
> > I would like to take an informal survey of what folks are
> commonly
> > specifying for standard signal via padstacks for 0.062"
thick, 1
> oz copper,
> > 2-4 layer boards.
> >
> > I am in the process of revamping our decal libraries to
comply
> with IPC
> > Level B producibility (as much as realistically possible)
and am
> troubled by
> > the 0.013" +/-0.003" Dia. finished hole / 0.025" Dia. pad
that
> was specified
> > by my predecessors. This doesn't even meet Level C and I
am
> concerned about
> > the possibility of breakout. However, to the best of my
> knowledge, breakout
> > with these vias has not been a problem in the past.
> >
> > Also, since this via is currently being used, I do not
want to
> increase the
> > pad size, but would rather decrease the finished hole
size. What
> is the
> > minimum finished hole size that won't drive up the cost
with your
> particular
> > fabricator?
> >
> > Your comments on this would be appreciated.
> >
> >
> > - Tom
> >
> >
> > *******************************************
> > Thomas A. Frayda, C.I.D.
> > PCB Designer
> > Detection Systems, Inc.
> > 130 Perinton Parkway
> > Fairport, NY 14450-9199
> > www.detectionsys.com
<http://www.detectionsys.com/>
> > www.dsworld.com <http://www.dsworld.com/>
> > TEL: 716-223-4060 x4365
> > FAX: 716-421-4263
> > E-mail: [log in to unmask]
> <mailto:[log in to unmask]>
> > *******************************************
> >
> >
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