I would like to attend. 
Thank you for arranging this for us.
Peggy Meadows
(408)765-5303


-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
Silicon Valley Chapter - IPC
Sent: Wednesday, February 22, 2006 8:21 PM
To: [log in to unmask]
Subject: [DC] Meeting Announcement: SIlicon Valley Chapter (March 14)

Silicon Valley Chapter of the IPC Designers Council
Our next meeting will take place on Tuesday, March 14
2006

Location:
Mentor Graphics
1001 Ridder Park Drive, San Jose, CA
March 14 Tuesday
Time: 11:30AM - 1:30PM
$1 for members; $5 for non-members
DOOR PRIZE: $25 IPC Publication Certificate

RSVP required > send to [log in to unmask]

Title:  Power System and I/O Breakout in Complex BGA
Designs

Speaker bio:  Mark Alexander, Senior Product
Application Engineer, Advanced Product Group, Xilinx
Inc.

Mr. Alexander is involved in the creation of design
rules and methodologies for power integrity assurance
in large FPGA systems at the die, package and PCB
levels. Mr. Alexander has been with Xilinx for seven
years, previously worked in areas of PCB design for
signal integrity and multi-gigabit transceiver
physical media attachment, and holds three patents.

http://dcchapters.ipc.org/svc/

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Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815
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