A few questions about testabaility (ICT and functional);

How far along in your design process does testabaility issues start?

Is anyone out there assigning properties to pins that are required for
testabaility (in symbol generation)?
If yes, How do the designers recoginize them?

Who defines critical pins? engineer, librarian, component eng., designer

Does anyone build seperate fan-out geoms for the same geom because of
testability? (per unique p/n, so you end up w/ 4 versions plcc20)
If yes, do you route on a standard grid or gridless?

Is each board routed with testabaility in mind, even if it is a minor volume
and may never reach a test bed?

Does anyone NOT ALLOW fan-outs under the component?


Thanks for your input,

Michael Kuczynski       Librarian/Sr. Designer
Allied Signal           201-393-2122 (Phone)
699 Rt46E E/K4          201-393-2357 (Fax)
Teterboro NJ 07608
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